Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-12-06
2003-03-04
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06528981
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a current mirror circuit used for a semiconductor integrated circuit and the like, and particularly to a cascode current mirror circuit that operates at a low voltage.
BACKGROUND ART
Generally, current mirror circuits are used as current amplifiers and the like for supplying output currents proportional to input currents. Further, in a case where it is required to supply an output current with high precision, a plurality of current mirror circuits are concatenated into a so-called cascode constitution to obtain a large output resistance.
FIG. 1
is a circuit diagram showing an exemplary structure of a general cascode current mirror circuit.
In
FIG. 1
, the current mirror circuit such as in a two-staged cascode constitution comprises four n-channel MOS transistors
11
to
14
, a current source
3
, and an output terminal
4
. In this circuit structure, a first stage current mirror circuit and a second stage current mirror circuit are made up by the n-channel MOS transistors
11
,
12
and the n-channel MOS transistors
13
,
14
, respectively, and the first stage current mirror circuit and the second stage current mirror circuit are mutually concatenated.
The current mirror circuit having such a constitution is input with an input current lin through a drain terminal of the n-channel MOS transistor
11
, to output an output current lo through a drain terminal of the n-channel MOS transistor
12
.
Assuming now that each of the n-channel MOS transistors
11
to
14
has a threshold voltage Vth and a value obtained by subtracting the threshold voltage Vth from a gate/source voltage Vgs of each of the n-channel MOS transistors
11
to
14
is &agr; (i.e., Vgs-Vth=&agr;; assuming that a drain current is equal to the input current lin), a gate voltage value of the n-channel MOS transistor
14
becomes Vth+&agr; and a gate voltage value of the n-channel MOS transistor
12
becomes
2
(Vth+&agr;).
FIG. 2
is a graph showing a relationship between an output voltage Vo and the output current lo in the current mirror circuit of FIG.
1
.
In
FIG. 2
, when a value of the output voltage Vo (a voltage of the output terminal
4
connected to the drain terminal of the n-channel MOS transistor
12
) is 2&agr; or less, each of the n-channel MOS transistors
12
,
14
operates in a non-saturation region (triode region); and when the value of the output voltage Vo is between 2&agr; and (Vth+2&agr;), the n-channel MOS transistor
12
operates in the non-saturation region and the n-channel MOS transistor
14
operates in a saturation region (pinch-off region). Further, when the value of the output voltage Vo is Vth+2&agr; or higher, each of the n-channel MOS transistors
12
,
14
operates in the saturation region. Namely, in the region where the value of the output voltage Vo is Vth+2&agr; or higher, an inclination of curve Vo-lo is extremely small to thereby attain an extremely large output resistance, so that the output current lo with high precision can be obtained.
However, to obtain the output current lo with high precision, the cascode current mirror circuit as described above is required to operate at an input voltage of 2(Vth+&agr;) or higher and at the output voltage Vo of Vth+2&agr; or higher, causing a problem of narrow settable ranges for the input/output voltages, and resulting in difficulty particularly in using the current mirror circuit in a low voltage circuit.
For example, as shown in
FIG. 3
, in a case where an output terminal of a p-channel cascode current mirror circuit is connected to an input terminal of an n-channel cascode current mirror circuit to thereby fold an electric current, since a voltage of 2(Vth
n
+&agr;
n
)+(Vth
p
+2&agr;
p
) or higher is required as a supply voltage Vc (in which subscripts
n
and
p
of respective parameters represent corresponding channels, respectively), for example, when Vth
n
=Vth
p
=1V and &agr;
n
=&agr;
p
=0.1V, these cascode current mirror circuits are unable to be used at a general supply voltage of 3.3V.
In view of the above, there has been proposed a circuit structure for lowering an input voltage and an output voltage, for example, a compound current mirror circuit known from U.S. Pat. No. 4,477,782 and the like.
Such as shown in
FIG. 4
, this compound current mirror circuit has a circuit structure in which an n-channel MOS transistor
11
′ and a current source
3
′ are, added to the current mirror circuit shown in
FIG. 1
, such that a ratio (W/L) of gate width to gate length in the n-channel MOS transistor
11
′ is ¼ times the W/L of each of other n-channel MOS transistors
11
to
14
.
In such a compound current mirror circuit, the gate voltage of the n-channel MOS transistor
12
becomes Vth+2&agr;. Thus, each of the n-channel MOS transistors
12
,
14
operates in the saturation region when the value of the output voltage Vo is 2&agr; or higher, as shown in FIG.
5
. Further, the voltage at the input terminal (i.e., the drain voltage of the n-channel MOS transistor
11
) becomes Vth+2&agr;. Thus, the input/output voltages required for the transistors to operate in the saturation region are lowered by an amount of the threshold voltage Vth, as compared with the cascode current mirror circuit of FIG.
1
.
However, the aforementioned compound current mirror circuit requires two current sources
3
,
3
′ with high precision at the input side, causing problems of complication of circuit structure and increase of the electric current consumption.
The present invention has been carried out in view of the aforementioned circumstances, and it is therefore an object of the present invention to provide a current mirror circuit capable of precisely operating even at low input/output voltages.
DISCLOSURE OF THE INVENTION
To this end, as shown in
FIG. 6
, a low voltage current mirror circuit according to the present invention including multiple (two in the illustrated example) circuit elements
1
A,
1
B, each forming a current mirror, and concatenating the circuit elements
1
A and
1
B to constitute a cascode current mirror circuit, comprises voltage dropping means
2
for mutually connecting inter-control-electrode nodes of each of the circuit elements
1
A,
1
B to cause the predetermined voltage drop &bgr; between the inter-control-electrode nodes.
According to such a circuit structure, by providing the voltage dropping means
2
, the control-electrode electric potential of the current mirror of the
1
circuit element
1
A becomes (Vth+&agr;)+&bgr;, to thereby lower an input voltage and an output voltage by (Vth+&agr;)−&bgr; as compared with the control-electrode electric potential 2(Vth+&agr;) in the conventional circuit structure.
The circuit elements
1
A,
1
B, as shown in
FIG. 6
, may be constructed such that: the circuit element
1
A includes an input transistor TR
1
and an output transistor TR
2
, and the circuit element
1
B includes an input transistor TR
3
and an output transistor TR
4
, each of the input transistors TR
1
, TR
3
and output transistors TR
2
, TR
4
provided with a first terminal, a second terminal, and a third terminal connected to a control-electrode, and a current mirror is formed by mutually connecting between the third terminals of the input transistor TR
1
and the output transistor TR
2
, and another current mirror is formed by mutually connecting between the third terminals of the input transistor TR
3
and the output transistor TR
4
; in the adjacent circuit elements
1
A,
1
B, the first terminal of the input transistor TR
3
is mutually connected to the second terminal of the input transistor TR
1
, and the first terminal of the output transistor TR
4
is mutually connected to the second terminal of the output transistor TR
2
; in the circuit element
1
A located at one end of the concatenation, the first terminal and the third terminal of the input transistor TR
1
are connected to each other,
Arent Fox Kintner Plotkin & Kahn
Patel Rajnikant B.
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