Low-voltage content addressable memory cell with a fast...

Details Low-voltage content addressable memory cell with a fast... Low-voltage content addressable memory cell with a fast...

2000-06-19

2001-05-29

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S154000

Reexamination Certificate

active

06240004

ABSTRACT:

SUMMARY OF THE INVENTION
The present invention is related to a novel low-voltage content addressable memory (CAM) cell with a fast tag-compare capability using partially-depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques.
BACKGROUND OF THE INVENTION
Content addressable memory (CAM) has been broadly used in many VLSI system applications such as imaging processing, network communication, and parallel data processing to facilitate operations of fast comparison and validation of patterns [J. B. Kuo and J. H. Lou, “Low-Voltage CMOS VLSI Circuits,” John Wiley: New York, ISBN 0471321052, 1999]. As shown in
FIG. 1
, in a conventional 10T CAM cell [H. Kadota, J. Miyake, Y. Nishimichi, H. Kudoh, and K. Kagawa, “An 8-kbit Content-Addressable and Reentrant Memory,” IEEE Journal of Solid-State Circuits, Vol. 20, No. 5, pp 951-957, 1985], it is composed of two portions: the SRAM portion (transistors M
1
-M
6
) and the tag-compare portion—transistors M
7
~M
10
for performing the XOR operation of the data stored in the SRAM cell with the input data at the digit lines.
Said SRAM portion comprises two PMOS's, designated as M
1
and M
2
; and four NMOS's, designated as M
3
, M
4
, M
5
and M
6
, wherein a drain of the NMOS M
3
is connected to that of the PMOS M
1
at a first node n
1
while their gates are tied together at a second node n
2
; a source of the PMOS M
1
is connected to a supply voltage V
DD
; a drain of the NMOS M
4
is connected to that of the PMOS M
2
at the second node n
2
while their gates are tied together at the first node n
1
; a source of the NMOS M
4
is grounded and that of the PMOS M
2
is connected to the supply voltage V
DD
; the NMOS M
5
and NMOS M
6
are pass transistors, one of them M
5
is controlled by a word line WL via its gate, and its drain and source are connected to a first bit line BL and the first node n
1
respectively; another one of them M
6
is controlled by the word line WL via its gate, and its drain and source are connected to a second bit line BLB and the second node n
2
respectively.
If logc-1 is stored at the internal storage node n
1
, which is different from the logic state of the data on the digit line (DL), then the match line (ML) is pulled down to ground, indicating a miss. Along with the increased complexity of the related VLSI systems, the speed performance of the tag-compare operation of a related large-size CAM circuit has become a bottleneck for high-speed applications, which is especially serious for operation using a low supply voltage. Recently, CMOS dynamic threshold (DTMOS) techniques have been reported for their advantages in low-voltage SOI CMOS VLSI circuits [F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,” IEEE Transactions on Electron Devices, Vol. 44, No. 3, pp 414-422, 1997; N. Lindert, T. Sugii, S. Tang and C. Hu, “Dynamic Threshold Pass-Transistor Logic for Improved Delay at Low Power Supply Voltages,” IEEE Journal of Solid-State Circuits, Vol. 34, No. 1, pp 85-89, 1999; I. Y. Chung, Y. J. Park, and H. S. Min, “A New SOI Inverter Using Dynamic Threshold for Low-Power Applications,” IEEE Electron Devices Letters, Vol. 18, No. 6, pp 248-250, 1997].
SUMMARY OF THE INVENTION
The present invention discloses a content addressable memory cell comprising a tag-compare portion comprising six NMOS transistors, designated as M
7
to M
12
, wherein
a source of M
7
is connected to a drain of M
8
, a drain of M
7
is connected to a match line, a source of M
8
is grounded; a body of M
7
and a body of M
8
are tied together at a source of M
11
, a gate of M
7
and a gate of M
11
are tied together to a first node n
1
, a gate of M
8
and a drain of M
11
are connected to a first digit line; and
a source of M
9
is connected to a drain of M
10
, a drain of M
9
is connected to said match line, a source of M
10
is grounded; a body of M
9
and a body of M
10
are tied together at a source of M
12
, a gate of M
9
and a gate of M
12
are tied together to a second node n
2
, a gate of M
10
and a drain of M
12
are connected to a second digit line.
Preferably, the content addressable memory cell of the present invention further comprises a SRAM portion containing said first node n
1
and said second node n
2
, wherein said SRAM portion comprises two PMOS's, designated as M
1
and M
2
; and four NMOS's, designated as M
3
, M
4
, M
5
and M
6
, wherein a drain of the NMOS M
3
is connected to that of the PMOS M
1
at said first node n
1
while their gates are tied together at said second node n
2
; a source of the PMOS M
1
is connected to a supply voltage V
DD
; a drain of the NMOS M
4
is connected to that of the PMOS M
2
at the second node n
2
while their gates are tied together at the first node n
1
; a source of the NMOS M
4
is grounded and that of the PMOS M
2
is connected to the supply voltage V
DD
; the NMOS M
5
and NMOS M
6
are pass transistors, one of them MS is controlled by a word line via its gate, and its drain and source are connected to a first bit line and the first node n
1
respectively; another one of them M
6
is controlled by the word line via its gate, and its drain and source are connected to a second bit line and the second node n
2
respectively.
In one of the preferred embodiments of the present invention, a novel low-voltage content addressable memory (CAM) cell with a fast tag-compare capability using partially-depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques was proposed. Using two auxiliary pass transistors (M
11
, M
12
) to dynamically control the bodies of transistors in the tag-compare portion of CAM cell, this SOI CAM cell has a fast tag-compare capability at a low supply voltage of 0.7V as verified by the MEDICI results.


REFERENCES:
patent: 5999435 (1999-12-01), Henderson et al.
patent: 6078513 (2000-06-01), Ong et al.
patent: 6157558 (2000-12-01), Wong
patent: 6175514 (2001-01-01), Henderson et al.

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