Low voltage constant current source

Details Low voltage constant current source Low voltage constant current source

2002-12-27

2004-09-21

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06794928

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to a low voltage constant current source with a reference current source and multiple current output units, and more particularly, each output current is individually amplified by a desired ratio to the reference current, and is independent from other output units to avoid any interference.
2. Description of Related Arts
With reference to
FIGS. 1A and 1B
, two different types of conventional current mirrors composed of bipolar transistors (BJTs) are respectively shown, wherein NPN transistors constitute the current mirror shown in
FIG. 1A
, and PNP transistors constitute that of FIG.
1
B. Basically, the circuit operations of the two current mirrors are similar. As shown in
FIGS. 1A and 1B
, because the bases of the two NPN transistors are connected together and emitters are both connected to ground, the junction voltage V
BE1
and V
BE2
are equal. In a condition that the two NPN transistors of
FIG. 1A
(or the PNP transistors in
FIG. 1B
) are matched, the input current I
1
(reference current) is approximately equal to the output current I
2
, wherein a partial current (designated with I
B
) of the input current I
1
is used to bias the two transistors. An approximate relationship between the two currents I
1
and I
2
is:
I
2
=I
1
×&bgr;/(&bgr;+2)
where &bgr; is called forward current gain, and the definition of which is &bgr;=I
C
/I
B
.
The typical value of &bgr; approximately lies between tens and hundreds, such as 50-250, and is varied with the size, the operating temperature or other manufacturing factors of the transistor. Obviously, the relationship between the input current I
1
and the output current I
2
is varied with &bgr;. When &bgr; value is getting smaller, I
B
is getting larger and the difference between I
1
and I
2
is accordingly increased.
For the current mirrors shown in
FIGS. 1A and 1B
, because the consumption of the input current I
1
is large, such a current mirror is unsuitable to configure a multi-stage current mirror.
If the ratio between the transistors in
FIG. 1A
or
1
B are not 1:1 but 1:N, the effect of current amplification is obtained, where the output current I
2
is expressed the equation I2≈N×I
1
. The precise equation is I
2
=I
1
×&bgr;N/(&bgr;+1+N). Therefore, when the value of N is getting closer to &bgr;, the current amplifying ratio &bgr;N/(&bgr;+1+N) is rapidly reduced. Such unmatched transistors will cause an extreme restriction on the current amplification of a current mirror. Moreover, limited by the manufacturing process of the bipolar transistors, the current mirror composed of bipolar transistors is only capable of providing an integer current amplification ratio, for example, 1:5, 2:3 or 10:7.
With reference to
FIGS. 2A and 2B
, two current mirrors composed of CMOS transistor are respectively illustrated, wherein NMOS transistors constitute the current mirror of FIG.
2
A and PMOS transistors are for FIG.
2
B. The operation of the CMOS current mirror is similar to the BJTs as mentioned above. When the two NMOS transistors (or PMOS) are matched, i.e. the channel width (W) and channel length (L) ratio (W/L) of the two NMOS transistors are identical, since the junction voltages between gate and source of the two NMOS transistors are the same (V
GS1
=V
GS2
) and there is almost no current flowing into the gates of the NMOS transistors (I
G
≈0), the input current I
1
is approximately equal to the output current I
2
. The error between the input and the output current is caused from that the output current I
2
is influenced by the output voltage V
DS2
. Thus, when V
DS2
is not equal to V
GS2
, a minor difference between I
1
and I
2
arises.
Since the channel width/length ratio (W/L) of the CMOS elements is programmable by properly controlling the design thereof, the non-integer current amplification ratio (I
2
/I
1
) is easily achieved by the CMOS current mirror. Furthermore, since the influence on the output current I
2
caused from the gate current is tiny, the CMOS current mirror is capable of providing a large current amplification ratio. However, the application of CMOS transistors is still limited by several factors, such as the low current driving ability, low transconductance (g
m
), low voltage endurance etc. Thus, when the CMOS current mirror is required to provide a high output current and a high voltage endurance, the CMOS transistors are usually manufactured to have a larger size than the BJT transistors, so the production cost is accordingly increased.
With reference to
FIGS. 3A and 3B
, two current mirrors with gain are respectively composed of NPN BJTs and PNP BJTs. Each current mirror further contains a gain transistor to provide a base current I
B
. The relationship between the input current I
1
and the output current I
2
is expressed by equation I
2
=I
1
×(&bgr;
2
+&bgr;)/(&bgr;
2
+&bgr;+2). Obviously, since the numerator and denominator of the equation both have &bgr;
2
, the constant 2 in the denominator is able to be omitted from the equation. The output current I
2
then is independent from &bgr; and almost equal to the input current I
1
.
However, the current mirrors shown in
FIGS. 3A and 3B
still have some problems in some particular operating conditions. For example, if the output of the current mirror is connected with a load and the output transistor is operated in the forward active region, the current mirror still functions normally. However, if the output of the current mirror is floating (i.e. there is no load connected to the output) or the output transistor is operated in the saturation region, a large current will flow through the gain transistor to the output transistor. Such a large current has some additional problems, such as power consumption and heat generation. Moreover, each transistor with base connected to the gain transistor is influenced and the output current is greatly decreased.
With reference to
FIGS. 4A and 4B
, a NMOS transistor (or a PMOS transistor in
FIG. 4B
) is applied to replace the BJT gain transistors as shown in
FIGS. 3A and 3B
. Since the gate current of the NMOS transistor is almost zero, the input current I
1
is independent. The base current for the two BJT transistors is completely supplied by the NMOS transistor (or the PMOS transistor). The advantage of such current mirrors is that the output current is independent of the &bgr; and operating temperature. Thus, if the current driving ability of the NMOS transistors is large enough, the current gain is able to be greatly increased.
However, the current mirrors shown in
FIGS. 4A and 4B
also suffer from the problems as mentioned of
FIGS. 3A and 3B
. When the output of the current mirror is floating, i.e. there is no load connected to the output, or the output transistor is operated in the saturation region, a large current will flow through the gain transistor to the output transistor.
Whether in
FIGS. 3A and 3B
or
FIGS. 4A and 4B
, since a gain transistor is additionally provided in the current mirror, an additional voltage is needed to bias the gain transistor. For example, the bias voltage for the current mirror in
FIG. 3A
is required to have V
BE
+V
BE
, and
FIG. 4B
requires V
BE
+V
GS
. Due to the additional bias voltage, the current mirror is unsuitable to be worked in the low operating voltage.
With reference to
FIG. 5
, a current mirror with multi current output units is mainly composed of BJTs and switching elements. Each switching element can be chosen from NMOS, PMOS or CMOS transmission gates. All the transmission gates must be identical and operated at the same bias voltage to ensure that each output unit is worked correctly. The transmission gate (the first one from the left) is always kept at conductive. Each output unit is equipped with a transmission gate, whereby each output current is independently determined by its own transmission gate.
If the possible floating problem oc

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