Low-voltage CMOS switch with novel clock boosting scheme

Details Low-voltage CMOS switch with novel clock boosting scheme Low-voltage CMOS switch with novel clock boosting scheme

2007-09-11

2007-09-11

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

Reexamination Certificate

active

10986630

ABSTRACT:
A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from VDDto (VDD+K×VDD). The voltage at the PMOS gate is decreased from VGNDto (VGND−k×VGND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=VGNDto VDD, even where VDDapproaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.

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Palmisano et al. “Clock Boosters for 1.2-V SC Circuits,” 1997 IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997, Hong Kong, vol. 3, Jun. 9, 1997, pp. 2012-2015.

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