Low-voltage CMOS phase-locked loop (PLL) for...

Details Low-voltage CMOS phase-locked loop (PLL) for... Low-voltage CMOS phase-locked loop (PLL) for...

2000-05-01

2001-09-18

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S008000, C331S025000, C327S156000, C327S157000

Reexamination Certificate

active

06292061

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a phase-locked loop (PLL), particularly to a PLL having a differential charge pump.
BACKGROUND
Among the continuing scaling of CMOS technology toward deep submicron range, the supply voltage is scaled to 1.5V to 1.8V range at current 0.18um to 0.15um manufacturing processes. Phase-Locked Loop (PLL) is one of the most important blocks for almost all high-performance digital chips such as CPUs, DSPs, communication transmitter/receivers, etc. However, as an analog circuit, PLL's control voltage range becomes more limited as the supply voltage becomes lower. Thus, a need exists for a CMOS PLL design for low-supply voltage and high-speed clock generation.
SUMMARY
The invention provides a CMOS phase-locked loop (PLL) design for low-supply voltage and high-speed clock generation.
Preferably, a PLL with a supply voltage Vdd includes a voltage controlled oscillator (VCO. The PLL also includes a loop filter coupled to the VCO. The loop filter has MOSFET gate capacitors with a process dependent threshold voltage of approximately Vth. Additionally, the loop filter has a first filter terminal with a first filter terminal voltage of Vf
1
and a second filter terminal with a second filter terminal voltage of Vf
2
. The PLL further includes a differential charge pump (CP) coupled to the loop filter, wherein the differential CP senses the threshold voltage Vth and maintains at a node a common-mode reference voltage of Vref that is approximately equal to (Vdd-Vth)/2. The differential CP has a common-mode feedback for centering Vf
1
and Vf
2
around Vref.


REFERENCES:
patent: 5933037 (1999-08-01), Momtaz
patent: 5945855 (1999-08-01), Momtaz
patent: 6188739 (2001-02-01), Everitt et al.

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