Low voltage CMOS analog switch

Details Low voltage CMOS analog switch Low voltage CMOS analog switch

2000-07-25

2002-12-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Parallel controlled paths

C327S427000, C327S576000, C327S437000

Reexamination Certificate

active

06492860

ABSTRACT:

FIELD OF THE INVENTION
The present disclosure relates to CMOS analog switches and more particularly to a low voltage, low leakage CMOS analog switch employing low threshold devices.
BACKGROUND OF THE INVENTION
Battery-powered operation and low voltage digital circuits have motivated the design of low voltage analog circuits. Analog integrated circuits are generally implemented using switched-capacitor techniques employing transmission gate switches. The ability of transmission gates to conduct reliably in the rail-to-rail range imposes a lower limit upon low voltage operation. The disclosed embodiments of a new transmission gate overcome this limitation and allow for operation with voltages as low as 1V.
A conventional CMOS transmission gate consists of an N-channel and a P-channel enhancement MOSFET connected in parallel. The respective drains and sources of the two transistors are tied together to become the switch terminals while the gates of the two transistors are usually driven to the power supply rails such that they are of complementary polarity. When the gate of the N-channel MOSFET is driven to the positive rail and the gate of the P-channel MOSFET is driven to the negative rail, the switch is on. When the gate of the N-channel MOSFET is driven to the negative rail and the gate of P-channel MOSFET is driven to the positive rail, the switch is turned off.
The “on” resistance of the transmission gate is a function of the device sizes, supply voltage, signal voltage and the threshold voltages of the MOSFETs. For the switch to have a finite “on” resistance over the entire range of the signal voltage, the sum of the magnitudes of the threshold voltages of the N-channel MOSFET and the P-channel MOSFET, V
TN
+|V
TP
|, must be less than or equal to the supply voltage. For low voltage operation (<1.5V), V
TN
+|V
TP
| is therefore constrained to be less than 1.5V over process and temperature variations. However, reducing the threshold voltages of the devices results in the exponential increase of the sub-threshold leakage when the transmission gate is turned off.
In order to ensure that sub-threshold leakage is negligible, it is necessary to keep V
TN
>0.5V and V
TP
<−0.5V over all process comers and temperatures. Given the typical process variations, these constraints are very difficult to achieve without unacceptable yield loss. It is generally not possible to satisfy both constraints simultaneously because the imposed limits are very tight over process variations and temperature. Moreover, for a 1.2V supply voltage, it is impossible to satisfy both threshold voltage constraints simultaneously.
Prior art solutions to this problem generally comprise increasing the gate voltage (i.e., clock multiplication) or reducing the leakage off-current. As disclosed in Bazarjani et al., “Low voltage SC Circuit Design with Low-V
t
MOSFETs”, known methods of reducing the leakage off-current include limiting the signal swing, adjusting V
T
by back bias, providing a series transmission gate switch and a parallel/series transmission gate. In particular, Bazarjani et al. disclose a parallel transmission gate using high V
T
MOSFETs along with a series transmission gate switch using low V
T
MOSFETs. The disclosed transmission gate does not however reduce leakage off-current in the case where the signal is close to or equal to the negative supply rail.
There therefore exists a need for an analog switch capable of low voltage operation which substantially reduces leakage off-current over the entire signal range.
SUMMARY OF THE INVENTION
A parallel/series transmission gate using high V
T
MOSFETs in the parallel transmission gate and low V
T
MOSFETs in the series transmission gate is useful for general purpose signal routing. The series transmission gate includes either a P-channel MOSFET, N-channel MOSFET, P-channel MOSFET series configuration or an N-channel MOSFET, P-channel MOSFET, N-channel MOSFET series configuration. The disclosed embodiments substantially reduce leakage off-current. For low threshold voltage N-channel MOSFETs having V
TN′
=V
TN
−&Dgr;V
TN
and low threshold voltage P-channel MOSFETs having |V
TP′
|=|V
TP
|−&Dgr;V
TP
, the minimum required supply voltage for the “on” condition is reduced by the lower of (&Dgr;V
TN
, &Dgr;V
TP
). Additionally, the leakage current of the series transmission gate is less than or equal to the leakage current of the parallel transmission gate for the same device geometries as long as the supply voltage is greater than &Dgr;V
TN
+&Dgr;V
TP
. To provide for both finite “on” resistance and low leakage current, both of the above constraints are satisfied and the resulting supply voltage is the lower of &Dgr;V
TN
+&Dgr;V
TP
and the minimum supply voltage reduced by the lower of (&Dgr;V
TN
, &Dgr;V
TP
).


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patent: 5506528 (1996-04-01), Cao et al.
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patent: 6154085 (2000-11-01), Ramakrishnan
patent: 6163199 (2000-12-01), Miske et al.

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