Low voltage CMOS analog multiplier with extended input dynamic r

Details Low voltage CMOS analog multiplier with extended input dynamic r Low voltage CMOS analog multiplier with extended input dynamic r

1997-08-12

1999-02-16

Nguyen, Matthew

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

330288, G05F 316, H03F 304

Patent

active

058724460

ABSTRACT:
A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.

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patent: 5587687 (1996-12-01), Adams
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