Low voltage buffer amplifier for high speed sample and hold...

Details Low voltage buffer amplifier for high speed sample and hold... Low voltage buffer amplifier for high speed sample and hold...

1999-05-12

2001-07-10

Pascal, Robert (Department: 2817)

Amplifiers

With periodic switching input-output

C330S253000

Reexamination Certificate

active

06259316

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a low voltage buffer amplifier, primarily for use in conjunction with high speed sample and hold (S/H) circuits.
BACKGROUND AND BRIEF DESCRIPTION OF THE PRIOR ART
A sample and hold circuit is usually employed in the front end of high speed flash and folding analog-to-digital (A/D) converters. Such A/D converters are widely used in modern communications and data storage integrated circuits. In such applications, the sample and hold (S/H) (either sample and hold or track and hold) circuit must drive a large array of comparators. This presents a large load capacitance and requires a high speed buffer amplifier at the output of the S/H circuit.
The circuit schematic diagram of a conventional prior art buffer amplifier suitable for high speed applications is shown in FIG.
1
. Two such buffers are typically used in a differential S/H circuit as shown in
FIG. 2
, one buffer for the positive terminal (Vinp) of the input and one for the negative terminal (Vinn) of the input. The buffer amplifier as shown in
FIG. 1
includes a simple differential amplifier M
1
and M
2
followed by source follower (transistor M
7
). The input Vb provides bias current for the entire amplifier. The simplicity of the circuit results in a high speed of operation. However, at low supply voltages, this circuit suffers from two problems: 1) there is insufficient headroom (voltage lower than the supply voltage) for the operation of the source follower transistor M
7
and 2) it to ensure that the tail current source, the current through transistor M
4
, is sufficiently deep into saturation at the full swing of the input signal. This results in a modulation of the tail current, causing harmonic distortion.
It is therefore readily apparent that there is a need for a buffer amplifier circuit usable for high speed S/H applications that addresses and minimizes the above described problems inherent in the prior art circuits.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a new low voltage buffer amplifier usable for data communications, data storage and other high speed applications which provides the above noted desired results.
Briefly, the above is accomplished by adding to the prior art amplifier as illustrated in
FIG. 1
an additional transistor (M
9
) controlled by the input voltage, Vin,in series with the second stage (M
5
, M
6
) and a capacitor level shifter (C
1
) between the output of the first stage (junction of M
2
and M
3
) of the amplifier and the gate termninal of the source follower transistor M
7
. This capacitor C
1
is charged such that the signal between the first stage and the source follower stage sees an upward dc voltage shift, thus maintaining the quiescent gate voltage for the source follower transistor M
7
close to or even higher than the supply voltage while maintaining the quiescent voltage at the output of the first stage (junction of M
1
and M
2
) sufficiently low for transistors M
2
and M
3
to operate in saturation regions.


REFERENCES:
patent: 4335355 (1982-06-01), Haque
patent: 4524329 (1985-06-01), Abou
patent: 4800339 (1989-01-01), Tanimoto et al.
patent: 4912425 (1990-03-01), Kobayashi et al.
patent: 5394111 (1995-02-01), Tsuji et al.
patent: 6049253 (2000-04-01), Takayama
patent: 6084476 (2000-07-01), Hamanishi et al.
patent: 0 448 169 (1991-09-01), None
patent: 0 598 308 (1994-05-01), None

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