Low voltage breakdown element for ESD trigger device

Details Low voltage breakdown element for ESD trigger device Low voltage breakdown element for ESD trigger device

2002-01-22

2004-03-23

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06710990

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to electrostatic discharge (ESD) protection semiconductor devices, and more particularly to diodes and MOS transistors used to dissipate ESD pulses. Specifically, the present invention relates to a low breakdown voltage diode and MOSFET operating to dissipate ESD pulses.
2. Description of the Related Art
As technology in the semiconductor industry advances, semiconductor devices shrink in size according to Moore's law. Shrinkage of semiconductor devices is desirable as smaller semiconductor devices allow smaller electronic equipment, use less power, run faster and provide more function for the same price. However, smaller devices can also be more susceptible to damage caused by electrostatic discharge.
Semiconductor devices are formed of three types of materials: conductors, insulators, and semiconductors, the latter of which can be controlled to change from a conductor to an insulator under various conditions. As the main materials used for conductors and insulators are metals (e.g., aluminum and copper) and oxides (e.g. silicon dioxide), and as the transistors operate by inducing electric fields in the semiconductor, the technology is referred to as MOSFET, short for metal-oxide-semiconductor field effect transistor, even though other materials can be used (e.g. heavily doped silicon and metal silicides can be used as a conductor).
FIG. 1A
shows a simple transistor
101
formed as a MOSFET device. Substrate
100
is a semiconductor that is formed of a conducting material having one of two types of polarity, either P-type or N-type. For purposes of this discussion, substrate
100
is a P-type substrate, although either type can be used. Regions
110
are non-conducting oxides that isolate this transistor from other transistors in the area. Regions
116
and
118
of substrate
100
are conductive regions with the opposite type of polarity, in this case, N-type. Generally one of regions
116
and
118
will be connected to a voltage source
117
and the other to a ground connection
119
, forming drain and source connections. Because a portion of the p-type substrate intervenes between regions
116
and
118
, a current cannot normally flow between these two regions. A gate
112
is constructed over the channel region
114
between source
116
and drain
118
, but electrically isolated from this region. By applying a voltage within a given range to gate
112
, an electric field is induced in channel region
114
immediately below gate
112
, which inverts the channel doping polarity from P-type to N-type, allowing a current to flow between the source and drain. The voltage applied to gate
112
can be controlled so that the transistor acts like a switch to turn the current on or off between the source and drain. A fourth terminal
115
of the MOSFET can connect to the substrate
100
, named the substrate or body connection. Circuits consist of thousands of these transistors, along with other semiconductor components. However, if a large enough voltage is applied to any of the gates, the gate insulation around the gate is destroyed and the necessary insulating properties of the MOS gate insulator are destroyed, causing the transistor to malfunction.
Diodes are another semiconductor device of interest. Rather than the five regions (gate, source, channel, drain and substrate) of a MOS transistor, a diode has only two regions (anode and cathode).
FIG. 1B
shows an example of a diode. Region
122
has the same type of polarity (e.g. P−) as substrate
100
, only a stronger concentration (e.g., P+), while region
120
has the opposite polarity (e.g., N+). A diode normally conducts electricity in only one direction. A diode is forward biased and conducts if the p-type side of the device is biased positive with respect to the n-type side (e.g., terminal
128
is connected to a positive voltage source while terminal
126
is connected to a ground source. A diode is reverse biased and does not conduct if the n-type side is biased positive with respect to the p-type side (e.g., terminal
128
is connected to a ground source and terminal
126
is connected to a positive voltage source). In the reverse bias condition, if the voltage is above a given value, called the breakdown voltage, the diode will conduct current. The reverse bias breakdown current is non-destructive as long as the current level is low enough to avoid heating the semiconductor or associated metal connections to damaging temperatures
Under the normal operating conditions of semiconductor devices, the currents and voltages that are established within the device are non-destructive. Under some conditions, the device can be exposed to very large voltages, generated by static electricity. When the device is subject to this static charge, the charge, known as an electrostatic discharge, or ESD, pulse, often finds a way to ground through the device. The high voltage can generate high currents for short periods of time. The high voltage is associated with a low charge; the voltage is not sustained and soon dissipates once it finds an easy path to ground. All semiconductor devices must be designed such that an ESD pulse does not damage the input, output, power, and ground devices. These components are designed so that the ESD protection devices will quickly recognize the ESD pulse and shunt the ESD pulse harmlessly to ground. If an ESD protection device is not available when the circuit is subject to an ESD pulse and once the pulse establishes the lowest resistance path to ground, high voltage levels will rupture and may cause permanent damage to the MOS gate oxides. High current paths will heat the silicon or metal conductors and cause permanent damage if they heat close to or above their respective melting points. In either mechanism, permanent device failure is likely to occur.
An integrated circuit requires a device that shunts an ESD pulse safely to a ground to prevent damage to its semiconductor devices. All ESD protection schemes work in this fashion.
Under normal high field operation of MOS devices, the field between the drain and channel can be high enough to create hole/electron pairs due to weak avalanche effects in the pinch-off region. The bias created by the holes can be enough to trigger parasitic bipolar conduction between drain and source. This parasitic conduction can also be induced by injecting any positive charge into the substrate of the MOS device. For this bipolar mechanism, the source, drain and substrate of the NMOS device operate as the collector, base and emitter of a lateral NPN bipolar device, and the injected charge is equivalent to the base current.
SUMMARY OF THE INVENTION
An electrostatic discharge circuit having an MOSFET and a diode is disclosed, along with the method of manufacturing the circuit. The diode and transistor are connected in parallel between a pad that normally carries an input or output signal and the grounded substrate, connected in such a manner that they cannot be turned on by the normal input or output signal voltage. However, whenever an electrostatic discharge event occurs, the voltage will exceed the reverse breakdown voltage of the diode. As breakdown current begins to flow through the diode into the substrate, the substrate of the MOS receives the potential necessary to turn the transistor on by parasitic NPN bipolar transistor action. The transistor will carry most of the current to ground, protecting the diode from overheating, while the tie to ground keeps the gate from receiving too high a potential and being destroyed. The electrostatic discharge is dissipated non-destructively. Once the ESD pulse has been discharged, both the diode and transistor return to their off state, ready for another ESD event.


REFERENCES:
patent: 4990802 (1991-02-01), Smooha
patent: 5043782 (1991-08-01), Avery
patent: 5140401 (1992-08-01), Ker et al.
patent: 5477414 (1995-12-01), Li et al.
patent: 5623156 (1997-04-01), Watt
patent: 5623387 (1997-04-01), Li et al.

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