Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-03-13
2002-06-18
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C323S312000, C323S313000
Reexamination Certificate
active
06407622
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates to constant voltage reference circuits. More particularly, the present invention relates to a bandgap voltage reference circuit wherein (i) the output voltage can be low and set relative to the silicon bandgap voltage, (ii) the output voltage can have a zero TC, and (iii) the operating supply voltage V
CC
can be limited.
B. Description of the Related Art
So-called bandgap reference circuit produces an output voltage that is approximately equal to the silicon bandgap voltage of 1.206 V (hereinafter termed simply the “bandgap voltage”) with a zero temperature coefficient (“TC”).
1. FIG.
1
—Prior Art
FIG. 1
shows a prior art bandgap reference circuit, sometimes called the Brokaw bandgap circuit. This circuit is built with current sources I
1
-I
2
, npn bipolar junction transistors Q
1
-Q
2
, resistors R
1
,-R
2
, and operational amplifier (“opamp”) A
1
. Opamp A
1
, has a negative input terminal (node n
1
,), a positive input terminal (node n
2
), and an output terminal (node n
3
).
Current sources I
1
-I
2
are implemented so that each current source produces a substantially equal current I. This can be done, for example, by utilizing p-channel MOS transistors. In such an implementation, the source of each PMOS transistor is connected to V
CC
, and the gates of the PMOS transistors are connected together in a current mirror configuration to node n
1
.
Transistor Q
2
is N times larger in size than transistor Q
1
. Initially, with Q
2
larger than Q
1
and equal current from I
1
-I
2
, the voltage across Q
1
will be N times larger than the voltage across Q
2
. Thus, node n
1
, will be driven higher than node n
2
. This will cause the voltage at node n
3
to increase. The bases of transistors Q
1
and Q
2
are connected to node n
3
, so increasing the voltage at node n
3
causes current I from current sources I
1
-I
2
to increase. Current I will increase until the voltage across resistor R
1
balances the voltage difference between transistors Q
1
and Q
2
.
The equilibrium value for the current I is given by
I
=
Δ
V
BE
R
1
(
1
)
The difference in the base-emitter voltage of the two transistors Q
1
and Q
2
is expressed as
Δ
V
BE
=
kT
q
·
ln
(
N
)
(
2
)
Because &Dgr;V
BE
is a function of thermal voltage kT/q, it is said to be proportional to absolute temperature (PTAT).
The output voltage V
out1
in
FIG. 1
is expressed as
V
out1
=
V
BE
1
+
2
·
R
2
R
1
·
Δ
V
BE
(
3
)
Three observations can be made about V
out1
. First, for a certain ratio of the resistors R
1
and R
2
, V
out1
becomes equal to the silicon bandgap voltage. Second, V
out1
does not depend on the absolute value of the resistors used, which is hard to control. Third, V
out1
is temperature independent—that is, it has a zero TC.
B. FIG.
2
—Prior Art
Most modem CMOS processes have only substrate pnp bipolar junction transistors available. In this case the collector of the pnp transistor is forced to be the VSS/ground node. The configuration for a bandgap reference circuit using this type of bipolar junction transistor is shown in FIG.
2
.
The circuit of
FIG. 2
is built with current sources I
3
-I
5
, pnp bipolar junction transistors Q
3
-Q
5
, resistors R
3
-R
4
, and opamp A
2
. Opamp A
2
has a negative input terminal (node n
4
), a positive input terminal (node n
5
), and an output terminal (node n
6
)
Current sources I
3
-I
5
are implemented so that each current source produces a substantially equal current I. As described above, this can be done by utilizing PMOS transistors.
Transistor Q
4
is N times larger in size than transistors Q
3
and Q
5
. Initially, with Q
4
larger than Q
3
and Q
5
and equal current from I
3
-I
5
, the voltage across Q
3
and Q
5
will be N times larger than the voltage across Q
4
. Thus, node n
4
will be driven higher than node n
5
. This will cause node n
6
to increase, causing the current I from current sources I
3
-I
5
to increase. Current I will increase until the voltage across resistor R
3
balances the voltage difference between transistor Q
4
and transistors Q
3
and Q
5
.
In this case, the output voltage V
out2
in
FIG. 2
is expressed as
V
out2
=
V
BE
5
+
R
4
R
3
·
Δ
V
BE
(
4
)
As with V
out1
in
FIG. 1
, V
out2
can be set equal to the silicon bandgap voltage, V
out2
is temperature independent, and V
out2
does not depend on the absolute value of the resistors used.
The prior art circuits of
FIGS. 1 and 2
cannot work with supply voltages below about 1.5 V, since the bandgap voltage with a zero TC is about 1.2 V for silicon. Many applications, however, require the voltage reference circuit to operate with a voltage supply below 1.5 V. The present invention presents such a circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, a bandgap voltage reference circuit is provided wherein (i) the output voltage can be a fraction of the silicon bandgap voltage, (ii) the output voltage can have a zero TC, and (iii) the operating supply voltage can be less than 1.5 V.
In one embodiment of the present invention, the prior art Brokaw bandgap circuit of
FIG. 1
is modified so that the operating supply voltage Vcc is lowered together with the output voltage by a constant offset. Referring to
FIG. 3
, the offset is created using an additional npn bipolar junction transistor (Q
2
), an opamp (A
3
) and a plurality of resistors (R
5
, R
6
and R
7
).
In further embodiments of the present invention, the prior art bandgap reference circuit of
FIG. 2
is modified so that the operating supply voltage is lowered together with the output voltage by a constant offset. In one embodiment, referring to
FIG. 4
, the offset is created using an additional current source I
6
, NMOS transistor M
3
, opamp A
4
, and resistors R
8
-R
10
. In another embodiment the offset is created, referring to
FIG. 5
, by modifying
FIG. 4
to omit current source I
6
, and the resistor R
4
shown connected in
FIG. 4
is moved to the emitter of transistor Q
5
.
REFERENCES:
patent: 4857823 (1989-08-01), Bitting
patent: 6150872 (2000-11-01), McNeill et al.
patent: 6204653 (2001-03-01), Wouters et al.
Fliesler Dubb Meyer & Lovejoy LLP
Lam Tuan T.
Nguyen Hiep
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