Low voltage analog-to-digital converters with internal...

Details Low voltage analog-to-digital converters with internal... Low voltage analog-to-digital converters with internal...

2000-03-29

2002-11-05

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000, C341S156000

Reexamination Certificate

active

06476751

ABSTRACT:

BACKGROUND
The present disclosure generally relates to analog-to-digital converters, and specifically to establishing internal reference voltage and offset in such converters.
In typical analog-to-digital (A-to-D) conversion, reference voltage levels are used to generate a digital representation of an analog input signal. Dynamic range/signal resolution is often maximized when the expected range of the analog input signal matches the reference voltage level.
FIG. 1
shows one type of A-to-D converter
100
that uses a technique known as successive approximation. The operation of this A-to-D converter
100
is analogous to weighing an unknown object on a laboratory balance scale as {fraction (1, 1/2, 1/4, 1/8)}, . . . 1
standard weight units. The largest weight is placed on the balance pan first; if it does not tip, the weight is left on and the next largest weight is added. If the balance does tip, the weight is removed and the next one added. The same procedure is used for the next largest weight and so on down to the smallest. After the n-th standard weight has been tried and a decision made, the weighing is finished. The total of the standard weights remaining on the balance is the closest possible approximation to the unknown weight. This weighing logic is implemented as a D-to-A converter
102
in FIG.
1
.
One embodiment of the successive approximation A-to-D converter
200
is illustrated in
FIG. 2. A
bank of capacitors
202
and switches
204
implement the weighing logic
201
with successively smaller size capacitors. A capacitor of size 2
n−1
*C represents the most-significant bit (MSB) while a capacitor of size C represents the least-significant bit (LSB). The value n is the number of binary bits in an A-to-D converter
200
. Maximum capacitance provided at the input signal node
214
is (2
n
−1)*C=C+ . . . +2
n−2
*C+2
n−1
*C. This is equivalent to a digital value of all ones. Therefore, the LSB voltage is
V
LSB
=
V
MAX
C
MAX
=
V
REF
(
2
n
-
1
)
*
C
.
An input signal (V
IN
)
206
is sampled onto the bank of capacitors
202
and a comparator
208
. Initially, the bottom plates of the capacitors
202
are grounded. During the conversion process, the bottom plates of the capacitors
202
are successively connected to the reference voltage (V
REF
)
210
. Corresponding bits are derived and stored in latches
212
.
A reference voltage level is generally adjusted and programmed to the input signal level. Since this reference voltage level is often adjusted to the full voltage swing of the input signal, the reference voltage must either be supplied to the A-to-D converter
200
from off-chip or generated on-chip using reference circuits.
SUMMARY
The present application defines an A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply.
The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.
The logic circuit is coupled to the comparator, and has successively smaller size capacitors. Each capacitor is connected to at least one switch. The switch is configured to successively connect each capacitor to different levels of the supply signal. The adjustable capacitor is also coupled to the comparator, and is configured to provide additional capacitance. The additional capacitance reduces full swing of the adjustable reference level to enable the logic circuit to operate with the supply signal.
The present application also defines a method of converting analog signal to digital signal. The method includes adjusting a reference capacitor at an input signal node to appropriately reduce full swing of a reference level. Conversion capacitors are selectively connected to a supply signal to program the reference level. The method also includes comparing an input signal to the programmed reference level, and reading a digital output value into latches if the comparison results in a match.


REFERENCES:
patent: 4200863 (1980-04-01), Hodges et al.
patent: 4517549 (1985-05-01), Tsukakoshi
patent: 5581252 (1996-12-01), Thomas
patent: 5606320 (1997-02-01), Kleks
patent: 5621409 (1997-04-01), Cotter et al.
patent: 5852415 (1998-12-01), Cotter et al.
patent: 5995036 (1999-11-01), Nise et al.

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