Low-voltage analog-to-digital converter

Details Low-voltage analog-to-digital converter Low-voltage analog-to-digital converter

1999-04-22

2001-03-06

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C327S063000

Reexamination Certificate

active

06198422

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog-to-digital (A/D) converter, and more particularly, to a low-voltage A/D converter which improves resolution by applying a sampling block at input terminal of a comparator to 0~Vdd period.
2. Discussion of the Related Art
Generally, industrial systems and controllers have trends to digital with the spread of CPUs having fast speed in an analog circuit at suitable cost. Most of industrial systems and controllers share digital mode with analog mode. In this respect, for signal transmission between digital mode and analog mode, analog-to-digital converter or digital-to-analog converter is required.
An analog-to-digital (A/D) converter is divided into an integrated mode and a comparative mode depending on a conversion mode. Since the comparative mode has a conversion speed faster than the integrated mode, it is mainly used in image processors and the like which require high conversion speed.
A background art A/D converter will be described with reference to the accompanying drawings.
FIG. 1
is a circuit diagram illustrating a background art flash A/D converter.
FIG. 2
is a block diagram illustrating a background art comparator.
FIG. 3
is a circuit diagram illustrating a background art NMOS transistor sampling block.
As shown in
FIG. 1
, a background art 4-bit flash A/D converter includes data input/output terminals consisting of a positive reference voltage input terminal
3
for inputting a positive reference voltage VREFP, a negative reference voltage input terminal
4
for inputting a negative reference voltage VREFN, a positive value input terminal
6
for inputting a positive input value INP, a negative value input terminal
5
for inputting a negative input value INN, and a digital data output terminal
7
, resistors R
1
~R
16
connected in series to sequentially level down the positive reference voltage and the negative reference voltage VREFN input through the data input/output terminals, comparators
2
a
~
2
o
for respectively comparing the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors R
1
~R
16
at a certain unit with the positive input value INP and the negative input value INN, and an encoder
1
for encoding the resultant value output from the comparators
2
a
~
2
o
and outputting the digital converted value.
In the 4-bit flash A/D converter of
FIG. 1
, the number of the comparators is 2
4
−1.
Each of the comparators includes a sampling block
8
for respectively sampling the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors R
1
~R
16
at a certain unit, the positive input value INP and the negative input value INN, an amplifier
9
for amplifying the sampled value, and a latch
10
for latching the positive value and the negative value output from the amplifier
9
.
The sampling block
8
of the comparator will be described with reference to FIG.
3
.
The sampling block
8
includes NMOS transistors NM
1
and NM
4
for switching the positive input value INP and the negative input value INN by an input operation clock PH
1
, NMOS transistors NM
2
and NM
3
for switching the positive reference voltage VREFP and the negative reference voltage VREFN by an operation clock PH
2
, capacitors C
1
and C
2
for storing and outputting sampling voltage values depending on selective turn-on/off of the NMOS transistors NM
1
, NM
2
, NM
3
and NM
4
, and NMOS transistors NM
5
and NM
6
turned on by applying an operation clock PH
3
at high to maintain output terminal of the sampling block
8
at AGND (ground) level and turned off by applying the operation clock PH
3
at low after sampling operation is completed, for outputting sampling values.
The sampling block
8
performs sampling operation by externally applied operation clocks PH
1
, PH
2
and PH
3
as follows.
If the operation clock PH
2
is applied at high under the state that the positive input value INP
1
and the negative input value INN
1
are maintained at AGND(ground) level by the operation clock PH
3
, the negative reference voltage VREFN and the positive reference voltage VREFP leveled down by the resistors R
1
~R
16
are sampled as follows.
INN
1
=
VREFN−AGND
INP
1
=
VREFP−AGND
Subsequently, if the operation clock PH
1
is applied at high and the operation clock PH
2
is applied at low, the input voltages INN and INP are sampled.
INN
1
=
INN
−(
VREFN−AGND
)
INP
1
=
INP
−(
VREFP−AGND
)
INN
1
and INP
1
sampled by the sampling block
8
are amplified through the amplifier
9
and output as digital values through the latch
10
.
The digital values sampled, amplified and latched in each of the comparators
2
a
~
2
o
are encoded by the encoder
1
and finally output as 4 bits.
Since the background art flash A/D converter includes the sampling block consisting of only NMOS transistors, it has several problems.
Input range of the NMOS transistor is 0~(Vdd−V
T
). In the current trend to low voltage of systems, it is impossible to use high input range by high V
T
, so that resolution of the A/D converter is deteriorated.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a low-voltage A/D converter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a low-voltage A/D converter which improves resolution by applying a sampling block at input terminal of a comparator to 0~Vdd period.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a low-voltage A/D converter according to the present invention includes: data input/output terminals consisting of input terminals for respectively inputting a positive reference voltage VREFP, a negative reference voltage VREFN, a positive input value INP and a negative input value INN, and digital data output terminals; resistors connected in series to sequentially level down the positive reference voltage VREFP and the negative reference voltage VREFN input through the data input/output terminals; comparators including a sampling block consisting of NMOS transistors and a sampling block consisting of PMOS transistors, for respectively comparing the positive reference voltage VREFP and the negative reference voltage VREFN leveled down by the resistors with the positive input value INP and the negative input value INN, wherein the sampling block consisting of NMOS transistors outputs the value of low bit and the sampling block consisted of PMOS transistors outputs the value of high bit comparators; and an encoder for encoding the resultant value output from the comparators and outputting the digital converted value.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5589785 (1996-12-01), Garavan

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