Low voltage amplifier

Details Low voltage amplifier Low voltage amplifier

2002-12-31

2004-08-24

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S253000

Reexamination Certificate

active

06781463

ABSTRACT:

FIELD OF INVENTION
The present invention relates to amplifiers. More particularly, the present invention relates to a low voltage amplifier.
BACKGROUND OF THE INVENTION
The demand for improved operational amplifiers, and in particular low power, operational amplifier circuits for high-precision data acquisition and instrumentation applications, such as multi-channel data acquisition systems, audio processing, test equipment and other consumer electronics applications continues to increase. Such operational amplifier circuits generally include an input stage circuit and an output stage circuit comprised of various amplifier devices and other current sources.
The input stage of many operational amplifier circuits, for example one comprising a differential pair arrangement of transistors, is configured for sensing a differential input voltage, which may realize inherent errors with offset voltage, bias current, offset voltage drift, and noise. The design of the input stage is typically aimed at minimizing these errors, while maintaining low current consumption, and with a large portion of the rail-to-rail input range being made available for common-mode signals.
Output stages are generally configured to provide a load impedance Z
L
with a desired output voltage V
OUT
and current I
OUT
, resulting in an output power P
OUT
=V
OUT
I
OUT
. The typical main requirements of output stages are to provide negative and positive output currents at high current efficiency, an output voltage range that efficiently uses the full rail-to-rail range, i.e., from the negative supply rail to the positive supply rail, low distortion, and good high-frequency performance.
Class-AB biasing is often used to improve performance of output stage devices due to the ability to eliminate cross-over distortion by biasing the output transistors at a small, but finite, current Class-AB biasing is similar to class-A biasing in that the output transistors are maintained “on”, and similar to class-B biasing in that the output transistors are biased at a much smaller current than the peak current delivered to the load. Class-AB biasing can be configured with feedforward biasing or with feedback biasing. Feedforward biasing is utilized when the biasing is fixed by components in series or in parallel with the signal path, while in feedback biasing uses a feedback loop to provide the class-AB biasing.
With reference to
FIG. 1
, an operational amplifier circuit
100
comprising an input stage
102
and an output stage
104
is illustrated as separate stages, which can be directly connected, or coupled through other stages. Such a class-AB configuration is often referred to as direct class-AB biasing.
Input stage
102
comprises a differential pair of transistors M
1
and M
2
. The difference in input current from a source I
1
, at the sources of transistors M
1
and M
2
is derived at the drains as signal currents, SIGNAL
1
, and SIGNAL
2
. Difference currents SIGNAL
1
, and SIGNAL
2
can be fed into multiple stage applications with appropriate level shifting, e.g., folded cascode or other stage applications, such as output stage
104
.
Output stage
104
comprises a class-AB biasing configuration including biasing transistors B
1
-B
4
, a pair of complementary signal devices M
3
and M
4
, and a pair of output devices, M
5
and M
6
. Output stage
104
is configured to source current in output device M
5
and to sink current through output device M
6
. It is desirable for output stage
104
to be able to fully swing from the positive rail to the negative rail, i.e., from V
S
+
to ground. This generally requires output devices M
5
and M
6
to be driven as common source devices. As common source devices, it is difficult to provide biasing when no current is flowing through output devices M
5
and M
6
. Further, when there is little or no output current at zero load, output devices M
5
and M
6
must still maintain a low dynamic output impedance. Without class-AB biasing, the output current could not go to zero, or the output impedance would be extremely high. However, the class-AB biasing configuration facilitates zero current under a zero load condition.
For example, biasing transistors B
1
and B
2
are connected in series and configured with a controlled current source I
2
to supply two gate-source voltages V
GS
to the gate of transistor M
3
. Transistor M
3
comprises a source follower that supplies current to the gate of transistor M
5
, thus providing a first, upper controlled V
GS
loop, with the gate-source voltages V
GS
of biasing transistors B
1
and B
2
equaling the gate-source voltages VGS of transistors M
3
and M
5
. The current flow within the upper V
GS
loop is defined by the areas and current flow within the devices. A current source I
4
is configured to provide a controlled current through transistor M
3
. Thus with controlled current provided through biasing transistors B
1
and B
2
and transistor M
3
, the current flow in transistor M
5
can be substantially controlled. Similarly, a second, lower controlled V
GS
loop is provided with biasing transistors B
3
and B
4
, transistor M
4
, and a controlled current source I
5
to control the nominal current flow in transistor M
6
.
During operation, when transistor M
5
sources (or supplies) more current, the gate-source voltage V
GS
of transistor M
5
increases; since the gate of transistor M
3
is constant, the gate-source voltage V
GS
of transistor M
3
must decrease, resulting in less current flow through transistor M
3
. Therefore, some of the current supplied to a node
106
must be diverted instead to transistor M
4
, resulting in the gate-source voltage V
GS
of transistor M
4
getting larger, thus decreasing or cutting off the gate-source voltage V
GS
of transistor M
6
, i.e., as transistor M
5
sources more current, transistor M
6
is cut off. Conversely, as transistor M
6
sinks (or requires) more current, transistor M
5
is cut off. For no load current, half of the current into node
106
flows through transistor M
3
and the other half through the drain of transistor M
4
to supply bottom current source
15
, resulting in nominal biasing of output devices M
5
and M
6
, i.e., a quiescent current condition with zero load current.
Unfortunately, for the upper and lower loops of output stage
104
to effectively bias the gates of transistors M
3
and M
4
at least two gate-source voltage V
GS
are needed. For typical CMOS processes, this two gate-source voltage V
GS
condition requires at least two volts or more, which is significantly higher than the low voltage operation, e.g., 1.8 volt or less, that is being demanded in current applications.
SUMMARY OF THE INVENTION
In accordance with various aspects of the present invention, an operational amplifier is configured for low voltage operation and better compliance. In accordance with an exemplary embodiment, an operational amplifier comprises a folded-cascode amplifier with a class-AB biased output stage configured for low voltage operation. The exemplary output stage includes a class-AB control loop being controlled for the upper output device, and with the complementary, lower output device being configured with an additional gain arrangement to allow for the necessary compliance voltage. The lower output device is configured to operate with a low gate-source voltage without significantly affecting the load impedance seen by a difference current received from an input stage. This configuration significantly increases the gain of the operational amplifier.
In accordance with an exemplary embodiment, the upper devices of the output stage can be configured with a cascoded mirror and a class-AB control loop driven by a charge pump to meet and/or exceed compliance voltage requirements for the upper devices.


REFERENCES:
patent: 4570128 (1986-02-01), Monticelli
patent: 5565815 (1996-10-01), Klein
patent: 6150883 (2000-11-01), Ivanov
patent: 6624696 (2003-09-01), Eschauzier et al.
Huijsing, Johan H., “Operational Amplifiers Theory And Design,” 2001, pp 322-324, “Compact 1.

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