1989-01-26
1989-10-24
James, Andrew J.
357 20, H01L 2980
Patent
active
048765791
ABSTRACT:
A JFET having top gate contact regions formed in either one or both of the source and drain regions at and contacting a substantial portion of the edge terminations of the top gate in the source and drain regions. The improved top gate contact region can be used in three and four terminal JFET's.
REFERENCES:
patent: 3223904 (1965-12-01), Warner, Jr. et al.
patent: 3649385 (1972-03-01), Kobayashi
patent: 4143392 (1979-03-01), Mylroie
patent: 4176368 (1979-11-01), Compton
patent: 4187514 (1980-02-01), Tomisawa et al.
patent: 4322738 (1982-03-01), Bell et al.
patent: 4456918 (1984-06-01), Beasom
patent: 4495694 (1985-01-01), Beasom
Beasom James D.
Davis Christopher K.
Harris Corporation
James Andrew J.
Prenty Mark
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