Low-to-high voltage translator with latch-up immunity

Details Low-to-high voltage translator with latch-up immunity Low-to-high voltage translator with latch-up immunity

1993-01-28

1994-06-14

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, H03K 1710

Patent

active

053213246

ABSTRACT:
A fast low-to-high voltage translator with immunity to latch-up. The circuit includes a voltage comparator and employs at least one transistor which is used to quickly pull up a node. If further uses another transistor which is capable of limiting the voltage at certain nodes in order to eliminate latch-up if a pumped power supply is provided to the circuit. Latch-up therefore is eliminated during power-up. Other transistors are utilized as voltage drop limiters to limit the voltage drop across other transistors during switching. This provides improved reliability by reducing substrate current and hot carriers.

REFERENCES:
patent: 4698526 (1987-10-01), Allan
patent: 4820941 (1989-04-01), Dolby et al.
patent: 4845381 (1989-07-01), Cuevas
patent: 4920284 (1990-04-01), Denda
patent: 5136190 (1992-08-01), Chern et al.
Foss et al., "Application of a High-Voltage Pumped Supply for Low-Power DRAM," 1992 Symposium on VLSI Circuits Digest of Technical Papers, vol., 11-1, pp. 106-107 (1992).

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