Low threading dislocation density relaxed mismatched...

Details Low threading dislocation density relaxed mismatched... Low threading dislocation density relaxed mismatched...

2001-01-16

2003-01-07

Nelms, David (Department: 2822)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Graded composition

C438S363000

Reexamination Certificate

active

06503773

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the field of low threading dislocation density relaxed mismatched epilayers, and in particular to such epilayers grown without high temperature.
The goal of combining different materials on a common substrate is desirable for a variety of integrated systems. Specifically, it has been a long-standing desire to combine different semiconductor and oxide materials on a common useful substrate such as a silicon substrate. However, just as the different materials properties are beneficial from the system application perspective, other properties may make such materials combinations problematic in processing. For example, semiconductor materials with different properties often have different lattice constants. Therefore, upon deposition of one semiconductor material on top of another substrate material can result in many defects in the semiconductor layer, rendering it useless for practical application.
Seminal work into the quantitative interpretation of dislocation densities and the connection to growth parameters was accomplished in the early 1990's (see, for example, E. A. Fitzgerald et al. J. Vac. Sci Tech. B 10,1807 (1992)). Using relaxed SiGe alloys on Si as the model system, it was realized that higher temperature growth of compositionally graded layers was a key to producing a relaxed SiGe layer on Si with high perfection.
However, practical constraints from current equipment used to manufacture Si-based epitaxial layers create difficulty in depositing high germanium concentration alloys without deleterious particle formation from either gas phase nucleation or equipment coating. For example, a large amount of current Si-based epitaxial wafers are created using single-wafer, rapid thermal chemical vapor deposition (CVD) systems. Although these systems offer great control of Si epilayer thickness uniformity across a wafer, the process encounters problems when germane is added to the gas stream to deposit SiGe alloy layers. Due to the lower decomposition temperature of germane than silane, dichlorosilane, or trichlorosilane, it is possible to nucleate germanium particles in the gas stream, or to coat parts of the reactor with thick deposits that can lead to particle generation.
The overall effect is that the epitaxial growth on the Si wafer can incorporate many particles, which not only degrade material quality locally, but also act as heterogeneous nucleation sites for additional threading dislocations, decreasing overall material quality. Particle generation occurs more rapidly with higher growth temperature; thus, the growth conditions that lead to lower threading dislocation densities (i.e. higher growth temperatures), unfortunately lead to more particles and a higher threading dislocation density than expected. Lower growth temperatures that avoid higher particle generation will create a higher threading dislocation density.
SUMMARY OF THE INVENTION
The problems of the prior art can be overcome by developing a method to create high dislocation velocities even though deposition occurs at lower growth temperatures. Accordingly, the invention provides a structure and a method to produce a low threading dislocation density, mismatched epilayer without the need for depositing the film at high temperature, thus avoiding the germane particle generation.
In accordance with an embodiment of the invention there is provided a semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer.
In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.


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