Low thrash cache with selectable tile geometry

Details Low thrash cache with selectable tile geometry Low thrash cache with selectable tile geometry

1994-08-02

1997-02-11

Swann, Tod R.

395445, 395340, 395509, 395515, G06F 1208

Patent

active

056029845

ABSTRACT:
A cache memory stores data from a source. Each item of data is identified by an address having a plurality of bits divided into four groups. A multiplexer responds to a control signal by selectively applying two of the groups of bits to address inputs of a tag memory and a random access memory, and selectively applying the other two groups of bits to a data input of said tag memory. The multiplexer enables different groups of address bits to address the two memories. A comparator compares a first set of bits formed by the other two groups of address bits to a second set of bits read from said tag memory. A memory controller causes data to be read from the random access memory when the first and second sets of bits match. When the first and second sets of bits do not match, the memory controller causes data to be read from the source and stored in the random access memory. In the latter instance, the tag memory stores the bits present at its data input.

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patent: 5056044 (1991-10-01), Frederickson et al.
patent: 5077678 (1991-12-01), Guttag et al.
patent: 5146592 (1992-09-01), Pfeiffer et al.
"Twenty-Five MHZ Logical Cache For A MC68020", Motorola Memories, Motorola, Inc, 1990, pp. 13-21 through 13-34.
"Designing A Cache For A Fast Processor", Electronic Design, Oct. 13, 1988, vol. 36, No. 23.

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