Low thermal expansion composite comprising bodies of...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material

Reexamination Certificate

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C257S703000, C257S758000, C257S762000, C257S764000, C257S763000, C257S765000, C252S700000, C252S700000, C252S700000, C252S700000, C252S299010, C252S700000, C428S616000, C428S618000, C428S620000, C428S615000, C428S637000, C428S639000, C428S644000, C428S650000, C428S652000, C428S653000, C428S663000, C428S664000, C428S674000, C428S668000, C428S671000, C428S661000, C428S660000

Reexamination Certificate

active

06326685

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to articles comprising low thermal expansion composite materials and their manufacture, in particular, those composites containing components, such as ductile alloy bodies, with negative coefficients of thermal expansion.
BACKGROUND OF THE INVENTION
Electronic devices and their package structures consist of a variety of metallic, ceramic, plastic or composite components with vastly different coefficients of thermal expansion (CTE). Mechanical or electrical failures in such devices are often caused by thermal expansion mismatch among the materials during fabrication or service. High thermal conductivity materials such as Cu and Al, and their alloys, are commonly used as heat sink materials in high-density, high-power-dissipating electronic packages. Differences in coefficients of thermal expansion (CTEs) between the heat sink material (e.g. 15-18 ppm/° C. for Cu and its alloys, 22-25 ppm/° C. for Al and its alloys, and about 8 ppm/° C. for the commonly used “low-expansion” 25% Cu-75% W composite) and the silicon chip (2.8-4.2 ppm/° C.) to which it is attached can cause stresses in the electronic package leading to complex thermal stress failure mechanisms. These thermomechanical problems can be thermoelastic, thermoplastic and elastoplastic deformations involving time-dependent and dynamic processes like stress rupture, thermal shock, thermal fatigue, creep and stress relaxation, and can seriously impair the reliability of the device. The thermal stresses induced by CTE mismatches can cause p-n junction failure in chips, brittle fracture in Si, Ga—As, or other semiconductor substrates, bowing or delamination of the layered assembly and stress corrosion failure in metals. Therefore, minimizing the mismatch between the heat sink material and semiconductor substrates can lead to significantly greater device reliability.
It is desirable to have heat sink materials with low CTE values, e.g., &agr;~4 ppm/° C., nearly matching that of silicon, or &agr;~6 ppm/° C., nearly matching that of Ga—As. Composite structures with low CTEs, e.g., layered configurations consisting of copper and low CTE materials such as tungsten (&agr;~4.5 ppm/° C.), molybdenum (&agr;~5.2 ppm/° C.), or Invar (Fe-36 w % Ni, &agr;~1.2 ppm/° C.) have been demonstrated. See, for example, Zweben et al,
Electronic Materials Handbook
, Vol. 1: Packaging (ASM, Metals Park, Ohio, 1989), p. 1129. However, the volume fraction of the non-copper metallic element generally needs to be substantial, e.g. of the order of 60-90 volume %, to significantly reduce the CTE value of copper, thereby reducing the efficiency of the heat sink.
Accordingly, there is a need for improved composite materials, especially those which can act as a heat sink for semiconductor substrates with a minimum of thermal mismatch.
SUMMARY OF THE INVENTION
In accordance with the invention, a reduced CTE composite structure is made by providing a matrix material whose CTE is to be reduced, adding negative CTE bodies to the matrix material and mechanically coupling the matrix material to the negative CTE bodies as by deforming the composite structure. A preferred application is to make an improved composite material for use as a heat sink for semiconductor substrates with a minimum of thermal expansion mismatch.


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