Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Reexamination Certificate
1999-06-09
2001-07-10
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
C174S257000, C174S258000, C174S260000, C257S702000, C257S766000, C428S901000
Reexamination Certificate
active
06258449
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a low-thermal expansion circuit board and a low-thermal expansion multilayer circuit board for bare chip mounting which have a small thermal expansion coefficient and are therefore highly reliable.
BACKGROUND OF THE INVENTION
With the recent tendencies for electronic equipment to have a smaller size and higher performance, it has been demanded for semiconductor devices constituting electronic equipment and printed circuit boards for mounting the devices to have reduced size and thickness, higher performance and higher reliability. To meet these demands, pin insertion mount is being displaced by surface mount, and, in recent years, a surface mount technology called bare chip mount has been under study, in which non-packaged (bare) semiconductor elements are directly mounted on a printed circuit board.
In bare chip mounting, however, because silicon chips having a thermal expansion coefficient of 3 to 4 ppm/° C. are directly mounted on a printed circuit board having a thermal expansion coefficient of 10 to 20 ppm/° C., stress is developed due to the difference in thermal expansion to impair the reliability. The stress causes joint fracture in, for example, flip chip bonding, which will lead to a faulty electrical connection.
In order to relax the thermal stress, it has been practiced to fill the gap between a mounted semiconductor element and a printed circuit board with an adhesive called an underfilling material thereby to disperse the stress imposed to the joint. In order for the stress to be absorbed by the printed circuit board itself, a multilayer printed circuit board having shear stress-absorbing layers between circuit layers to provide a stepwise gradation of thermal expansion coefficient in its thickness direction has been proposed (see JP-A-7-297560). However, reliability achieved by these techniques is still insufficient. It is indispensable for securing further improved reliability to diminish the thermal expansion coefficient of the printed circuit board itself.
In this connection, JP-A-61-212096 teaches a multilayer circuit board comprising an Fe—Ni alloy substrate having alternately formed thereon insulating layers and wiring conductors and, if desired, having solder pads formed on the top layer thereof by photoetching, the substrate, the insulating layers and the wiring conductors being united into an integral laminate by pressure bonding under heat. The technique disclosed has the following disadvantages. Where copper is used as a wiring conductor, it is difficult to reduce the thermal expansion coefficient of the whole circuit board to the level of silicon because the elastic modulus of copper is far greater than that of a polyimide resin used as an insulating layer. The wiring conductor is formed by thin metallic film formation techniques, such as vacuum deposition and sputtering, which have low productivity and incurs increased cost. Formation of solder pads by deposition followed by photoetching requires complicated steps.
On the other hand, the increasing I/O pin count of semiconductors to be mounted has increased the necessity of laminating a plurality of circuit boards. A multilayer circuit board can be produced by a build up method comprising alternately building up, on one or both sides of a substrate, insulating layers of a photosensitive resin and conductor layers formed by plating or deposition. The build up method is disadvantageous in that the production process is complicated and involves many steps, the yield is low, and much time is required.
JP-A-8-288649 proposes a method for producing a multilayer circuit board comprising forming protrusions of conductive paste by means of a dispenser, etc. on the copper side of a single-sided copper-clad epoxy/glass laminate, pressing an adhesive sheet and copper foil thereto, and repeating these steps. This technique is unsatisfactory in reliability of electrical connection, connection resistivity, and the like, and is hardly applicable to fine circuits. Further, it is a time-consuming method that the step of pressing must be repeated as many times as the number of the layers.
The inventors of the present invention have found that the above-described problems associated with conventional techniques are chiefly caused by the extremely greater thermal expansion of the board, more specifically, the organic materials making up the insulating layer, such as an epoxy resin and a polyimide resin, and copper as a wiring material, than that of semiconductor elements. Copper, which is commonly used as a wiring conductor, has not only a large thermal expansion coefficient but a large modulus of elasticity to increase the stress of thermal expansion. Notwithstanding, copper is an excellent electrically conductive material and has come to be indispensable as a wiring material.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a low-thermal expansion circuit board and a low-thermal expansion multilayer circuit board which have a small thermal expansion coefficient and are excellent in reliability.
The above object is accomplished by a low-thermal expansion circuit board comprising an insulating layer made of an organic polymer having thereon a wiring conductor for bare chip mounting, wherein the wiring conductor comprises an iron-nickel-based alloy layer having a copper layer on at least one side thereof.
The object is also accomplished by a multilayer circuit board having a plurality of the above-described low-thermal expansion circuit boards laminated integrally.
In the practice of the present invention, the multilayer circuit board has a plurality of double-sided circuit boards integrally laminated with an adhesive layer interposed between every adjacent circuit boards, the adhesive layer having through-holes at positions connecting the wiring conductors of the adjacent upper and lower double-sided circuit boards, and the through-holes containing a conductor made of solder by which the wiring conductors of the adjacent double-sided circuit boards are electrically connected.
As a result of extensive study, the inventors have developed a highly reliable low-thermal expansion circuit board by using a composite wiring material composed of an iron-nickel-based alloy layer having a low thermal expansion coefficient and a copper layer provided on at least one side of the alloy layer. Copper wiring, which is the chief cause of the great thermal expansion of the circuit board, being directly formed on an iron-nickel-based alloy layer having a low thermal expansion coefficient, the stress on thermal expansion of the wiring conductor can be reduced. As a result, thermal expansion of the circuit board as a whole can be suppressed thereby to bring about improved reliability of bonding after bare chip mounting.
The thermal expansion coefficient of the insulating layer, which is another cause of the great thermal expansion of the circuit board, can be reduced by using a polyimide resin prepared from pyromellitic acid dianhydride (hereinafter abbreviated as PMDA), m-tolidine (hereinafter abbreviated as m-TLD), and diaminodiphenyl ether (hereinafter abbreviated as DDE) which has a small thermal expansion coefficient. The reliability of the circuit board can thus be enhanced further.
Where the insulating layer made of an organic polymer contains a core made of an iron-nickel-based alloy or a ceramic material, the thermal expansion coefficient of the insulating layer can further be reduced.
Laminating the low-thermal expansion circuit boards of the present invention provides a multilayer circuit board having the above-mentioned advantages.
REFERENCES:
patent: 4769270 (1988-09-01), Nagamatsu et al.
patent: 5120573 (1992-06-01), Miyazaki et al.
patent: 5153986 (1992-10-01), Brauer et al.
patent: 5322976 (1994-06-01), Knudsen et al.
patent: 5723206 (1998-03-01), Higashi et al.
patent: 61-212096 (1986-09-01), None
patent: 64-16836 (1989-01-01), None
patent: 7-297560 (1995-11-01), None
patent: 8-288649 (1996-11-01), None
Inoue Yasushi
Nagasawa Megumu
Nakamura Kei
Sugimoto Masakazu
Lam Cathy
Nitto Denko Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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