Low-temperature process metal-to-metal antifuse employing silico

Details Low-temperature process metal-to-metal antifuse employing silico Low-temperature process metal-to-metal antifuse employing silico

1992-12-17

1994-12-13

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Non-single crystal, or recrystallized, active junction...

257530, H01L 2702, H01L 2946

Patent

active

053731697

ABSTRACT:
A metal-to-metal antifuse includes a lower electrode formed from a first metal layer in a semiconductor or other microcircuit structure. A barrier layer is disposed over the first metal layer. A first heavily-doped amorphous silicon layer is disposed over the barrier layer. A thin dielectric antifuse material is disposed over the first amorphous silicon layer. This dielectric can be nearly any dielectric such as nitride or oxide or a combination of these materials such as ONO and should have a breakdown voltage suitable for programming inside the integrated circuit. A second heavily-doped amorphous silicon layer is disposed over the dielectric layer. An upper electrode, comprising a second metal layer including an underlying barrier layer, is disposed over the second amorphous silicon layer. The first and second metal layers may comprise metal interconnect layers in the circuit structure.

REFERENCES:
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5166556 (1992-11-01), Hsu et al.

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