Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2002-11-04
2004-09-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S618000
Reexamination Certificate
active
06787885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of direct wafer bonding.
2. Description of the Prior Art
Hydrophobic wafer bonding is a method of joining two silicon wafers together, preferably with an electrically transparent junction. The wafers are pressed together without an adhesive. This is an efficient method of building device structures that make use of conduction through the bond interface. Among the possibilities for the use of hydrophobic wafer bonding is fabricating full wafer devices such as silicon controlled rectifiers (SCR) and thyristors. The more advanced device designs utilize hydrophobic bonding of processed wafers in order to produce devices with features on both sides. This eliminates the difficulties of processing both sides of a single wafer. Hydrophobic wafer bonding has been proposed and proven as a method of fabrication of double-sided double-gate insulated gate bipolar transistors (DIGBT). The DIGBT structure has been proven to both lower the switching time and losses in power device applications over a traditional IGBT structure.
A primary concern with wafer bonding is voids at the bond interface. There are two primary categories of interfacial voids: extrinsic and intrinsic. Extrinsic voids appear immediately after bonding and are the result of particles, surface imperfections, or air trapped at the interface. Intrinsic bubbles are thermally generated and form after annealing the bonded wafers. Particulate contamination related voids are a factor of the cleanliness of the processing facility. The contamination related voids are eliminated by careful processing and cleanliness procedures and stringent water filtration systems. Analysis of the gases in thermally generated voids indicates the presence of water, nitrogen, hydrocarbons, and hydrofluoric acid. The main constituent, however, is hydrogen from the hydrophobic hydrogen-terminated silicon. Monohydrides have been shown to desorb at 447° C., while dihydrides will desorb at 367° C. The most common way to eliminate the thermally generated voids is to anneal the bonded wafers at high temperatures (800-1000° C.). The high-temperature anneal allows the gases to diffuse into the bulk of the bonded wafers.
With whole wafer device structures such as the thyristor, annealing the bonded wafers at high temperature may be possible, however, if either of the wafers has device processing on it, there may be a strict thermal budget that will not allow annealing over approximately 450° C. depending on the metallization used.
Hydrophilic bonding is not an acceptable method when an electrically transparent junction is needed. Hydrophilic bonding leaves native oxide on the surfaces of the wafers. This native oxide affects the electrical properties of the junction between the wafers. On the other hand, hydrophobic bonding removes the native oxide, allowing for the possibility of an electrically transparent junction.
Kub et al., U.S. Pat. Nos. 6,194,290; 6,153,495; and 6,274,892, incorporated herein by reference, disclose a method of hydrophobic direct wafer bonding comprising the steps of processing two semiconductor substrates, bonding the substrates, and annealing the bonded substrates. The annealing is done at a low temperature, such that the processed surface is not damaged. For example, the annealing temperature is below the melting point or the reaction temperature of a metal on the processed surface. Strong bonds can be formed by this method. A disadvantage of this method is that voids form in the bond interface during the annealing step. Although the regions between the voids may be electrically transparent, the voids are non-conducting carrier traps that reduce the breakdown voltage of the interface, so that it is not electrically transparent throughout the entire bonding interface. Generally, as the number of voids increases, the strength of the bond decreases. When the wafers are cut into individual devices, any device that has a void in its bond may be unusable. As the number of voids increases, the yield of usable devices decreases.
There is need for a method of direct wafer bonding of processed wafers that results in an electrically transparent bond interface that is free of voids, and is strong enough to withstand subsequent handling or dicing.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of direct wafer bonding that produces a strong, electrically transparent junction.
It is a further object of the invention to provide a method of direct wafer bonding that does not produce voids in the bond interface.
It is a further object of the invention to provide a method of direct wafer bonding that does damage the features of the wafers.
It is a further object of the invention to provide a method of direct wafer bonding that improves yields over prior methods and over double-sided processing.
These and other objects may be accomplished by a method of making an electronic device comprising the steps of: providing a plurality of wafers, each wafer comprising a bonding surface; etching one or more trenches into one or more bonding surfaces, the trenches substantially perpendicular to a preferred direction of diffusion along one or more of the bonding surfaces; rendering the bonding surfaces hydrophobic; and bonding the bonding surfaces together by direct wafer bonding.
The invention further comprises a semiconductor structure comprising a plurality of wafers, each wafer comprising a bonding surface, one or more bonding surfaces comprising one or more trenches substantially perpendicular to a preferred direction of diffusion along one or more of the bonding surfaces; and the bonding surfaces bonded together by a direct wafer bonding interface.
REFERENCES:
patent: 6010591 (2000-01-01), Gosele
patent: 6194290 (2001-02-01), Kub et al.
patent: 2002/0030285 (2002-03-01), Sawada et al.
Desmond, Hobart, Kub, Campisi, and Weldon (“Low-temperature atmospheric silicon-silicon wafer bonding for power electronic applications,” Electrochemical Society Proceedings, 1998, vol. 97-36, p. 459-465).*
Kub, Hobart, and Desmond (“Electrical characteristics of low temperature direct silicon-silicon bonding for power device applications,” Electrochemical Society Proceedings, 1998, vol. 97-36, p. 466-472).*
Hobart, Kub, Dolny, Zafrani, Neilson, Gladish, and McLachlan (“Fabrication of a Double-Side IGBT by Very Low Temperature Wafer Bonding,” Proceedings of the 11th International Symposium on Power Semiconducotr Devices and ICs, 1999. ISPSD '9 1999, p. 45-48.*
Esser, Hobart, and Kub, “Improved Low Temperature Hydrophobic Si-Si Bonding Techniques,” abstract published on internet prior to Sep. 6, 2001.*
Esser, Hobart, and Kub (“Improved Low Temperature Hydrophobic Si-Si bonding Techniques,” presentation to Electrochemica Society Meeting, San Francisco, CA, Sep. 6, 2001).*
Esser, Robert,“Improved Low Temperature Hydrophobic Si-Si Bonding Techniques”, Internet, prior to Sep. 6, 2001.
Esser, Robert,“Improved Low Temperature Hydrophobic Si-Si Bonding Techniques”, Electrochemical Society Meeting, San Francisco, CA Sep. 6, 2001.
Hobart, K.D., Fabrication of a Double-Side IGBT by Very Low Temperature Wafer Bonding, IEEE, 1999, pp. 45-48.
Desmond, Cynthia A, “Low-Temperature Atmospheric Silicon-Silicon Wafer Bonding For Power Electronic Applications”, Electrochemical Soceity Proceedings, vol. 97-36, pp. 459-465.
Fritz, J, “Electrical Characteristics of Low Temperature Direct Silicon-Silicon Bonding For Power Device Applications”, Electrochemical Society Proceedings, vol. 97-36, pp. 466-472.
Esser, Robert, “Directional Diffusion and Void Formation at a Si (001) bonded wafer interface”, Journal of Applied Physics, Aug. 15, 2002, pp. 1945-1949, vol. 92 No. 4.
Esser Robert H.
Hobart Karl D.
Kub Francis J.
Flynn Nathan J.
Grunkemeyer Joseph T.
Karasek John J.
Quinto Kevin
The United States of America as represented by the Secretary of
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