Low temperature cobalt silicidation process monitor

Details Low temperature cobalt silicidation process monitor Low temperature cobalt silicidation process monitor

1998-06-25

2003-10-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S017000, C438S018000

Reexamination Certificate

active

06635501

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor processing and more particularly relates to temperature monitoring in rapid thermal processing systems in order to control the formation of silicides for contacts and conductive lines in semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
As the feature size of semiconductor integrated circuits continue to decrease, the necessity of decreasing the resistance and capacitance associated with interconnection paths (i.e., contacts) and conductive lines becomes more critical. For example, in a MOS transistor structure, the RC delay due to the interconnect paths can exceed the delays due to gate switching. Therefore the higher the RC product, the more likely a circuit's operating speed will be limited by the delay. Consequently, low resistivity interconnections and conductive lines are crucial in order to fabricate dense, high performance integrated circuit devices.
One solution to the above problem of contact resistivity is the use of silicides (e.g., WSi
2
and TiSi
2
). Silicides exhibit a reduced resistance as compared to polysilicon and are easy to form (e.g., via direct metallurgical reaction, co-evaporation, sputtering or chemical vapor deposition (CVD)). Although silicides may be formed at differing stages of the semiconductor manufacturing process, suicides are often formed after formation of the MOS structure using a self-aligned silicide (“salicide”) process, which is illustrated in prior art
FIGS. 1
a
-
1
e.
As illustrated in prior art
FIG. 1
a
, a MOS transistor
10
is bounded by outside isolation regions
12
. The transistor
10
includes a gate
14
and a gate oxide
16
which overlies a substrate
18
and separates the substrate
18
into a source region
20
and a drain region
22
. A source
24
and a drain
26
are formed in the source region
20
and the drain region
22
, respectively, through the gate oxide
16
to form shallow junctions.
As illustrated in prior art
FIG. 1
b
, the oxide
16
is removed in the source region
20
and the drain region
22
and insulated sidewall spacers
28
are formed on the lateral edges of the gate
14
and the gate oxide
16
. A conductive film
30
(the type of conductor will depend on the type of silicide desired) is then formed over the transistor
10
, as illustrated in prior art
FIG. 1
c
, and subjected to thermal processing. The thermal processing causes the conductor/silicon interface regions to react, thereby resulting in the formation of a source silicide
32
in the source region
20
, a drain silicide
34
in the drain region
22
and a gate silicide
36
on the gate
14
as shown in
FIG. 1
d
. The sidewall spacers
28
do not experience a reaction with the conductive layer during thermal processing and prevent the shorting of the source
24
in the drain
26
to the gate
14
via the silicide. The unreactive conductive material is then removed with an etchant that does not attack the silicides, as illustrated in prior art
FIG. 1
d.
A dielectric layer
38
is then deposited over the transistor
10
and contact holes are formed down to the source silicide
32
, the drain silicide
34
and the gate silicide
36
, respectively. A conductive contact layer (e.g., aluminum) is then formed and etched to form contacts
40
a
,
40
b
and
40
c
, as illustrated in prior art
FIG. 1
e
. The resistivity is greatly reduced since the sheet resistance of the resulting silicide is about 1-2 ohms/square whereas the sheet resistance of the diffused junctions without the silicide is about 40-120 ohms/square.
The thermal processing utilized to form the silicides is preferably rapid thermal processing (RTP) to prevent significant diffusion of the source
24
and drain
26
and thereby maintain shallow junctions. The sheet resistance of the resulting silicides are strong functions of the annealing temperature. Consequently, a tight control of the RTP temperature is desired. Several prior art type temperature monitors have been utilized to monitor the temperature within the RTP chamber. The RTP apparatus itself incorporates a thermal sensor; however, the apparatus utilizes closed-loop control, therefore the apparatus always indicates the desired temperature and does not provide a secondary, independent monitoring system. Consequently, any calibration or internal system errors in the apparatus remain undetected. Temperature sensors such as thermocouples have also been utilized. Thermocouples, however, measure only the temperature of the gas within the chamber and do not accurately measure the reaction temperature at the silicon/conductor interface which dictates the resulting silicidation reaction and sheet resistance.
Another prior art method of monitoring the RTP silicidation temperature uses a temperature sensor called a pyrometer. A pyrometer measures the temperature of an object by measuring the quantity of thermal radiation from an object's surface and converting it to a surface temperature. Therefore the relationship between the thermal radiation and the temperature is dependent upon the emissivity of the surface. Pyrometers experience difficulty because many detect emissivities in limited wavelengths and ignore emissivities in other regions of the spectrum. This assumes that emissivity occurs at a constant level across the frequency spectrum which is an erroneous assumption.
In addition, the amount of energy reflected and absorbed from the surface is highly dependent on the type of wafer film and furthermore is highly dependent on the position along the wafer surface. Differences in the types of material and their thicknesses result in variability in the absorption and reflectivity of local areas on the wafer surface which results in variations in emissivity at different regions of the semiconductor wafer. Consequently, pyrometers do not accurately indicate the temperature at the silicon/conductor interface which governs the resulting silicide sheet resistance.
Another prior art method for monitoring RTP process temperatures includes measuring a sheet resistance of a film after thermal processing. These type of monitors, however, have primarily focused on high RTP temperature ranges above 650° C. As RTP process temperatures continue to decrease to maintain ultra shallow junctions, no accurate sheet resistance monitors have been developed.
Therefore it is desired to generate an accurate method for monitoring the temperature of silicidation processes.
SUMMARY OF THE INVENTION
The present invention relates to a method for monitoring a temperature in a rapid thermal processing (RTP) step. The method utilizes the silicidation reaction of a cobalt film on silicon by measuring the resultant cobalt silicide sheet resistance to determine the reaction temperature at the cobalt/silicon interface.
According to one aspect of the present invention, a cobalt film is deposited onto a silicon wafer and a RTP step is performed at a desired target temperature, thereby generating a cobalt silicide. A cobalt silicide sheet resistance measurement is taken and the actual RTP temperature is determined using a sheet resistance-temperature transformation curve.
According to another aspect of the present invention, a cobalt film sheet resistance measurement is taken prior to the silicidation to take into account the post silicidation sheet resistance dependence on the pre-RTP sheet resistance. The actual RTP temperature is then determined using either a three dimensional sheet resistance-temperature plane or surface.


REFERENCES:
patent: 4764026 (1988-08-01), Powell et al.
patent: 5225366 (1993-07-01), Yoder
patent: 5436494 (1995-07-01), Moslehi
patent: 5460451 (1995-10-01), Wadman
patent: 5624590 (1997-04-01), Fiory
patent: 5690429 (1997-11-01), Ng
patent: 5714392 (1998-02-01), Dawson et al.
patent: 6002109 (1999-12-01), Johnsguard et al.
Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, 1990, pp. 150-152.

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