Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
2000-04-28
2002-03-26
Mis, David (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S143000
Reexamination Certificate
active
06362697
ABSTRACT:
TECHNICAL FIELD
This invention relates to a low supply voltage oscillator circuit, and, more specifically, this invention relates to a circuit that can generate an oscillating signal that is independent of the supply voltage, temperature of operation and the process used to create the circuit, and can work with a low supply voltage.
BACKGROUND OF THE INVENTION
Oscillator circuits are widely used in analog and digital circuits. They can be employed in a large number of applications, such as for driving a voltage multiplier, or generating a clock frequency or a programmable delay.
A good oscillator is usually expected to be operable at a high switching frequency and to have an oscillation frequency independent of the supply voltage, process variations, and temperature. It is also expected to have a duty cycle which can be defined for a constant ratio, and to exhibit low electromagnetic interference (EMI), that is, primarily voltages edges with controlled slopes of moderate steepness.
In recent years, there has been an increased demand for devices capable of operating on lower supply voltages, e.g., for cellular telephone and computer applications, and increased demand for more efficient performance, e.g., for the processing of signals in a synchronous state machine, which must be managed at a very high clock frequency.
A very simple oscillator circuit
1
is shown in FIG.
1
. It is formed by connecting into a loop two inverters INV
1
′, INV
2
′, a resistor R
0
, and a capacitor C
0
, and generates an oscillating electric signal of substantially square shape.
The oscillator circuit
1
has the following frequency of oscillation:
f
0
=
1
R
0
C
0
·
[
ln
(
V
S
+
V
TH
V
TH
)
+
ln
(
V
S
+
V
TH
V
S
-
V
TH
)
]
(
1
)
where,
V
S
is the supply voltage to the oscillator circuit
1
; and
V
TH
is the switching voltage threshold of the inverters INV
1
′ and INV
2
′.
This simple circuit fails, however, to meet the aforementioned requirements. In particular:
the oscillation frequency is dependent on the switching voltage threshold of the inverters: its value reaches a maximum when the switching voltage threshold of the inverters is one half the supply voltage;
the duty cycle of the oscillator circuit
1
also is dependent on the switching voltage threshold of the inverters: its value is 50% when the switching voltage threshold of the inverters is one half the supply voltage; and
the voltage at the input of the first inverter INV
1
′ has larger variations than the circuit supply voltage: its value varies between V
TH
+V
S
and V
TH
−V
S
.
From an article by S. Hobrecht, “An Intelligent BiCMOS/DMOS Quad
1
-A High-Side Switch”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, Dec. 1990, especially from FIG.
4
and its description on page 1397, a more sophisticated oscillator circuit
2
is known, as shown schematically in FIG.
2
.
The oscillator circuit
2
includes a first inverter INV
1
and a second inverter INV
2
which are cascade connected to each other and connected to an output terminal OUT of the oscillator circuit
2
, and two similar symmetrical sections connected to form a double feedback loop between the input terminal of the first inverter INV
1
and the output terminal OUT of the oscillator circuit
2
.
A first of the sections includes a first transistor SW
1
of the P-channel MOS type and a first current generator GEN
1
, which are connected in series with each other between a supply terminal VDD and a ground voltage reference GND. In addition, the first transistor SW
1
has a control terminal connected to the output terminal OUT.
The first section also includes a first capacitor C
1
connected in parallel with the first current generator GEN
1
and connected to the ground reference GND, and includes a first controlled switch SW
3
which is connected between the first capacitor C
1
and the input terminal of the first inverter INV
1
.
To provide for the circuit feedback, the control terminal of the first controlled switch SW
3
is connected to an interconnection node X between the first INV
1
and second INV
2
inverters.
Likewise, the oscillator circuit
2
includes a second section, which in turn includes a second capacitor C
2
having first and second terminals, a second current generator GEN
2
having an input terminal and an output terminal, a second transistor SW
2
of the N-channel MOS type, and a second controlled switch SW
4
, in a circuit configuration which is similar to that just described for the first section.
Where the two capacitors C
1
and C
2
have the same capacitance Co and the generators GEN
1
and GEN
2
have the same current value Io, the oscillation frequency of the oscillator circuit
2
will be:
fo
=
Io
V
S
·
Co
(
2
)
Thus, the oscillator circuit
2
is not affected by the problems brought about by dependence of the oscillation frequency on the switching voltage threshold of the inverters, and on a varying input voltage to the first inverter.
However, not even this solution is entirely devoid of drawbacks. In particular:
the oscillation frequency is dependent on the supply voltage VDD;
the duty cycle is dependent on the switching voltage threshold of the inverters; and
the oscillation frequency and duty cycle are both affected by any asymmetry existing between the current generators GEN
1
and GEN
2
, since they are formed in practice by P-channel and N-channel transistors.
A further approach is described in European Patent No. 0 735 677 to this Applicant, herein incorporated by reference, wherein, as shown schematically in
FIG. 3
, a single capacitor C is used which is charged and discharged by two current generators (Gen
1
, Gen
2
) having first and second values, such that the voltage across the capacitor C will follow a triangular pattern and have an amplitude which corresponds substantially to the ratio of the product of the two values and their sum.
In particular, the oscillator circuit
3
includes a capacitor C, charge circuitry CCA, and control circuitry CCO.
The charge circuitry CCA includes the first and second current generators, GEN
1
and GEN
2
, which generate two current values with opposite signs to deliver current at the output of the circuitry CCA and absorb it. It also includes a switch means, represented by first SW
1
and second SW
2
switches operative to alternately couple the generators GEN
1
, GEN
2
to the capacitor C.
The control circuitry CCO has a voltage input coupled to the capacitor C and an output coupled to control inputs of the switches SW
1
, SW
2
, and includes a comparator with hysteresis.
An oscillating signal appears at several points of the oscillator circuit
3
which can be utilized to output, for example, the voltage across the capacitor C. However, it is convenient to have the circuit output OUT connected to the output of the comparator with hysteresis, that is, to the output of the circuitry CCO, so that a substantially square wave-like form can be obtained. This square wave normally needs no buffering because the output of a comparator has relatively low impedance.
The circuitry CCO has an input and an output, and includes two comparators COMP
1
, COMP
2
, an inverter COMP
3
, two controlled switches SW
3
, SW
4
, and first and second voltage generators VTH and VTL.
The oscillator circuit
3
has essentially two operational conditions: a first condition which corresponds to the capacitor C being injected the current from the generator GEN
1
, and a second condition which corresponds to the capacitor C being extracted the current drawn by the generator GEN
2
.
The circuitry CCO is adapted to alternatively activate the first or the second operational condition according to whether the voltage across the capacitor C has dropped below the lower threshold or exceeded the upper threshold.
The oscillation frequency of the oscillator circuit
3
is substantially:
f
0
=
1
R
0
C
0
(
3
)
Thus, the oscillation frequency and duty cycle of the oscillator circuit
3
are dissociated from the supply voltage, the temp
Iannucci Robert
Jorgenson Lisa K.
Mis David
Seed IP Law Group PLLC
STMicroelectronics S.r.L.
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