Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-06-18
1999-05-11
Le, Vu A.
Static information storage and retrieval
Floating gate
Particular biasing
36518511, 36518518, 3651852, 36518911, G11C7/00
Patent
active
059034980
ABSTRACT:
The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.
REFERENCES:
patent: 4967399 (1990-10-01), Kuwabara et al.
patent: 5333122 (1994-07-01), Ninomiya
patent: 5528536 (1996-06-01), Baldi et al.
Roubik Gregorian et al., "Analog MOS Integrated Circuits for Signal Process," in a Wiley Series on Filters, Design, Manufacturing, and Applications, Wiley-Interscience Publication, New York, New York.
Campardo Giovanni
Commodaro Stefano
Micheloni Rino
Carlson David V.
Le Vu A.
STMicroelectronics S.r.l.
Tarleton E. Russell
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