Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-01-02
2003-09-09
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S065000, C330S258000
Reexamination Certificate
active
06617888
ABSTRACT:
FIELD
The invention pertains generally to differential signal drivers. More particularly, one embodiment of the invention relates to transistor-based low voltage differential signaling driver circuits.
BACKGROUND
Various types of data transmission schemes, within a device or between two or more devices, have been developed.
One type of data transmission is differential data transmission in which the difference in voltage levels between two signal lines forms the transmitted signal. For example, differential data transmission is commonly used for data transmission rates greater than 100 Mbps over long distances.
Driver circuits are employed to place and drive signals on a transmission line or medium. Low voltage differential signaling (LVDS) drivers are commonly employed in many applications including driving signals from a transmitter to a receiver. Typical LVDS drivers may permit high speed transmissions, use low power, have low electromagnetic interference (EMI), and are low in cost.
An example of a conventional LVDS driver circuit
100
is shown in FIG.
1
. The difference in voltage between the output signals OUT+ and OUT− form the pair of differential signals. A pair of differential signals means two signals whose current waveforms are one hundred eighty degrees (180°) out of phase with one another.
The LVDS driver circuit
100
includes a first direct current (DC) constant current source I
1
coupled to a voltage supply V
DD
, two p-channel metal oxide semiconductors (PMOS) P
1
and P
2
, two n-channel metal oxide semiconductor (NMOS) N
1
and N
2
(differential pairs), and a second DC constant current source I
2
coupled between a common node COM and ground. The our differential pair transistors P
1
, P
2
, N
1
, and N
2
are controlled by input voltage signals D+ and D− and direct current through load resistor R
LOAD
as indicated by arrows A and B. The input voltage signals D+ and D− are typically rail-to-rail voltage swings.
The operation of the LVDS driver circuit
100
is explained as follows. Two of the four transistors P
1
, P
2
, N
1
, and N
2
turn ON at the same time to steer current from current sources I
1
and I
2
to generate a voltage across resistive load R
LOAD
. To steer current through resistive load R
LOAD
in the direction indicated by arrow A, input signal D+ goes high turning ON transistor N
1
and turning OFF transistor P
1
, and input signal D− simultaneously goes low turning ON transistor P
2
and turning OFF transistor N
2
.
Conversely, to steer current through resistive load R
LOAD
in the direction indicated by arrow B, input signal D− goes high to turn ON transistor N
2
and turn OFF transistor P
2
, input signal D+ goes low to turn ON transistor P
1
and turn OFF transistor N
1
. As a result, a full differential output voltage swing can be achieved.
Differential LVDS driver circuit
100
works well as long as the output voltage swing stays within the allowable common mode voltage range, usually a few volts.
This driver
100
has the advantage of providing good power supply rejection. Common-mode voltage V
CM
is established by an external bias voltage through resistor R
1
. Ideally, common-mode voltage is maintained at a certain level or within a certain range. In many driver applications, a common-mode of 1.25 volts is employed.
One disadvantage of this driver
100
is that it requires higher power supply levels to keep the transistors properly biased. The transistors that form the current sources I
1
and I
2
must have sufficient voltage across them to be in saturation. The differential pairs P
1
, P
2
and N
1
, N
2
have a minimum voltage drop associated with the output current and channel resistance. Finally, all of this has to remain properly biased throughout the output signal swing range. Some margin must be added to allow the driver to work over all process, voltage and temperature (PVT) variations. This biasing requirement applies to the CMOS circuit shown or for bipolar junction transistors. For example, a typical LVDS push-pull driver requires at least a 2.5-volt supply to remain properly biased around a 1.25-volt nominal common-mode level.
Thus, the supply voltage level required by conventional LVDS drivers restrict development of lower power applications and devices with power supplies lower than 2.5 volts.
REFERENCES:
patent: 4105942 (1978-08-01), Henry
patent: 5475323 (1995-12-01), Harris et al.
patent: 5856757 (1999-01-01), Eschauzier
patent: 5859564 (1999-01-01), Sonntag et al.
patent: 5933056 (1999-08-01), Rothenberg
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 6166563 (2000-12-01), Volk et al.
patent: 6329843 (2001-12-01), Hirata et al.
patent: 6369621 (2002-04-01), Tinsley et al.
patent: 6414557 (2002-07-01), Liu
patent: 0812068 (1997-12-01), None
patent: 0938187 (1999-08-01), None
patent: WO 9828886 (1998-07-01), None
US patent application, Ser. No. 09/451,684, entitled “Input-Output Bus Interface,” by Dabral et al.
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