Low supply voltage analog multiplier

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

Reexamination Certificate

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Details

C327S359000, C327S589000

Reexamination Certificate

active

07061300

ABSTRACT:
The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

REFERENCES:
patent: 4978924 (1990-12-01), Schuster
patent: 5302868 (1994-04-01), Fergus
patent: 5467046 (1995-11-01), Kimura
patent: 5742199 (1998-04-01), Shoji et al.
patent: 5764559 (1998-06-01), Kimura
patent: 5883539 (1999-03-01), Kimura
patent: 5886560 (1999-03-01), Kimura
patent: 5886916 (1999-03-01), Muraoka
patent: 6456142 (2002-09-01), Gilbert
patent: 6563365 (2003-05-01), Knierim et al.
patent: 0 296 131 (1988-12-01), None

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