Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-04-15
2004-06-22
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
Reexamination Certificate
active
06753591
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an inductor, and more particularly, to a low substrate loss inductor manufactured by semiconductor IC technologies.
2. Description of the Prior Art
Passive elements, such as inductors or transformers, are widely used in microwave or high frequency wireless communication circuits. With the progress of semiconductor IC technologies and the requirement of small-sized, low-cost, and highly integrated systems, passive elements are integrated gradually in a single chip. Inductive elements are generally designed on a substrate with high impedance or on a substrate without energy loss, such as, a gallium arsenide (GaAs) substrate, for obtaining high quality factor and high self-resonance frequency inductors. However, because of the high cost, a low impedance silicon substrate (resistivity from 0.01 to 10 ohm-cm) is generally used to reduce the chip cost.
Please refer to
FIG. 1
to FIG.
3
.
FIG. 1
is a schematic diagram of a silicon substrate inductor
13
of the prior art.
FIG. 2
is a cross-sectional diagram of the silicon substrate inductor
13
shown in
FIG. 1
along line
2
—
2
.
FIG. 3
is a schematic diagram of an equivalent circuit of the silicon substrate inductor
13
shown in
FIG. 1. L
s
and R
s
represent the inductance and the resistance of the inductor
14
respectively, C
ox
is the parasitic capacitance between the inductor
14
and the substrate
10
, and C
sub
and R
sub
represent the parasitic capacitance and the resistance generated by the substrate
10
. As shown in FIG.
1
and
FIG. 2
, the inductor
14
is formed by a spiral metal coil, and an insulation layer
12
is installed between the inductor
14
and the substrate
10
to isolate the inductor
14
and the substrate
10
. Generally the material of the isolation layer is silica (SiO
2
). The inductor
14
comprises two ends, wherein the current flows in from one end and flows out from the other. If the current of the inductor
14
flows clockwise, a magnetic field that passes through the substrate
10
will be generated, therefore a counterclockwise image current (also called eddy current)
18
will be generated on the substrate
10
. The image current
18
will result in energy loss.
Please refer to
FIG. 4
to FIG.
6
.
FIG. 4
is a schematic diagram of a patterned ground shield (PGS) inductor
21
.
FIG. 5
is a cross-sectional diagram of the inductor
21
shown in
FIG. 5
along line
5
—
5
.
FIG. 6
is a schematic diagram of an equivalent circuit of the inductor
21
shown in FIG.
4
. For simplifying description, same index numbers are used to indicate same elements in the figures. Because the image current
18
causes energy loss, a PGS
16
is formed by a polysilicon or a metal layer between the inductor
14
and the substrate
10
to avoid the energy loss as shown in FIG.
4
and FIG.
5
. The banded conductive wires of the PGS
16
are separated by trenches and arranged orthogonal to the direction of current flow of the inductor
14
so that the image current
18
generated by the magnetic field of the inductor
14
can be avoided. Further the energy loss of the substrate
10
can be reduced and the quality factor of the inductor
14
can be increased. The PGS
16
can avoid the image current
18
generated by the magnetic field of the inductor
14
. However, the distance between the inductor
14
and the PSG
16
is shortened, that enlarges the parasitic capacitance of the inductor
14
, decreases the self-resonance frequency of the inductor
14
, and reduces the frequency application range of the inductor
14
. Because C
ox
enlarges, the parasitic capacitance of a PSG inductor is larger than the parasitic capacitance of a silicon substrate inductor of the prior art. Moreover, the self-resonance frequency is inversely proportional to the square root of the product of parasitic capacitance and inductance of the inductor
14
, therefore the higher the parasitic capacitance and the inductance are, the less the self-resonance frequency of the inductor
14
is.
Thus it can be seen that in the silicon substrate inductor
13
of the prior art, the image current
18
generated by the magnetic field of the inductor
14
would cause energy loss that will reduce the quality factor of the inductor
14
. Though the PGS
16
formed by a polysilicon or metal layer can avoid the image current
18
generated by the magnetic field of the inductor
14
, it also reduces the distance between the inductor
14
and the PGS
16
, that enlarges the parasitic capacitance of the inductor
14
. The enlargement of the parasitic capacitance would decrease the self-resonance frequency of the inductor
14
, and reduce the frequency application range of the inductor
14
.
SUMMERY OF INVENTION
It is therefore a primary object of the claimed invention to provide a low substrate loss inductor manufactured by IC technologies to solve the above-mentioned problem.
According to the claimed invention, an inductor comprising a substrate, a plurality of P-type and N-type doping strips alternatively formed inside the substrate, an isolation layer formed on the substrate, and a metal coil formed on the isolation layer is provided. The isolation layer isolates the metal coil and the plurality of P-type and N-type doping strips, and the plurality of P-type and N-type doping strips is arranged orthogonal to the metal coil.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 6452249 (2002-09-01), Maeda et al.
Hsu Winston
Nguyen Cuong
VIA Technologies Inc.
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