Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-03-21
2004-08-17
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010
Reexamination Certificate
active
06777969
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to the field test modes, and particularly to method and apparatus for providing a low stress test mode.
BACKGROUND OF THE INVENTION
The testing of semiconductor devices is utilized to insure product reliability before shipment of the device. The process is generally termed a “burn-in” process, in which the device is stressed to test the operation of the device. Semiconductor device failure rates as a function of time indicate that devices that survive an initial testing period operate reliably during the contemplated life span of the device. Thus, to promote device integrity, early failures in marginal and defective devices may be forced before the devices are sent to assembly plants for packaging, final testing, and the like.
To lower the period of time needed to test the device, the burn-in process may include power and temperature extremes to test for semiconductor device failure. For example, super voltage test modes may utilize high voltages to save time and money by utilizing power extremes to encourage failures in devices to occur sooner. However, super-voltages may damage some devices more than other devices coupled to a circuit.
For instance, super voltage test mode entry for use in test modes during burn-in may require high voltages, such as greater than 2.5 volts above the power supply test voltage applied to the gates of an input buffer to enter and remain in test mode. The additional 2.5 volts above power supply are required to prevent spurious test mode entry due to power supply noise. For example, with power supply test voltages of 7 volts, greater than 9.5 volts is applied to the gates of an input buffer to enter and remain in test mode. The high voltage stress may cause voltage shifts on an input buffer device, which may result in problems during normal device operations. If other components are available on a circuit, there are no viable alternatives to testing the device and ensuring integrity of devices on the circuit. For example, devices may not be adequately tested due to the desire to prevent damage to susceptible devices, such as an input buffer, or a susceptible device may be stressed to the point of causing failure during normal operation.
Therefore, it would be desirable to provide a method and apparatus for providing low stress test modes.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus and method for low stress test modes. In a first aspect of the present invention, a method of performing a low stress test mode includes applying an initial voltage in an amount sufficient to perform a device burn-in to a first device and a second device. Voltage at the second device is reduced, wherein voltage is reduced at the second device while voltage at the first device is at an amount sufficient to perform device burn-in.
In a second aspect of the present invention, a low stress test circuit includes a voltage supply. The voltage supply is suitable for providing voltage in an amount sufficient to perform a test mode burn-in. A first device and a second device are coupled to the voltage supply. A voltage stress reducer is positioned between the second device and the voltage supply, the voltage stress reducer suitable for reducing voltage at the second device from an initial voltage level supplied by the voltage supply to the second device to a reduced voltage level, while voltage at the first device remains at an amount sufficient to perform device burn-in.
In a third aspect of the present invention, a low stress test circuit includes a means for supplying test voltage. The test voltage supply means is suitable for providing voltage in an amount sufficient to perform a test mode burn-in. A first device and a second device are coupled to the test voltage supply means. A means for reducing voltage stress is also included, the voltage stress reducing means positioned between the second device and the test voltage supply means, the voltage stress reducing means suitable for reducing voltage at the second device from an initial voltage level supplied by the test voltage supply means to the second device to a reduced voltage level while voltage at the first device remains at an amount sufficient to perform device burn-in.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
REFERENCES:
patent: 4961053 (1990-10-01), Krug
patent: 5070297 (1991-12-01), Kwon et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5701666 (1997-12-01), DeHaven et al.
patent: 5929651 (1999-07-01), Leas et al.
patent: 5999390 (1999-12-01), Cho et al.
Cypress Semiconductor Corp.
Karlsen Ernest
Marger & Johnson & McCollom, P.C.
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