Low stress semiconductor devices with thermal oxide isolation

Details Low stress semiconductor devices with thermal oxide isolation Low stress semiconductor devices with thermal oxide isolation

1997-04-17

2001-10-30

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S506000, C257S647000

Reexamination Certificate

active

06310384

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device as typified by a semiconductor memory device, its fabrication method and its design method. More particularly, the present invention relates to a semiconductor device suitable for a high integration density semiconductor device, its fabrication method and its design method.
In the development of a high integration density semiconductor device, efforts at reducing the size of a device isolation region for electrically isolating adjacent device formation regions has been a critical problem.
A thermal oxide film has been generally used for forming this device isolation region. To locally form the thermal oxide film, a silicon nitride film is deposited on the surface of the device formation region and then a thermal oxidation reaction is carried out. This thermal oxidation reaction proceeds due to diffusion of an oxidation seed, that is, oxygen or steam vapor, and due to a reaction on the interface between an oxide film and a semiconductor substrate.
Because diffusion of the oxidation seed takes place three-dimensionally, such diffusion is extended also to a location below the silicon nitride film at which location the oxide film is not desired to be formed. Because the shape of growth of the oxide film below the silicon nitride film has a shape of the beak of a bird, it is generally referred to as a “bird's beak”. The growth of the bird's beak reduces an area of the device formation region. Therefore, restriction of this growth is important towards accomplishing a high integration density.
To restrict the growth of the bird's beak, a technology which forms grooves on a semiconductor substrate near the end portion of the silicon nitride film and oxidizes the inner wall of the grooves to form the device isolation regions has been developed in the past. A concrete method is described in JP-A-3-96249 and JP-A-4-127433, for example.
The silicon nitride film used as an anti-oxidaton film generally has a great internal stress. Therefore, a high stress occurs in the proximity of the semiconductor substrate surface, too. When a shear stress component (resolved shear stress) in a direction of a slip plane of a crystal [(
111
) crystallographic plane in the case of a Si crystal] exceeds a limit value, dislocation occurs, and electric characteristics of a device are remarkably deteriorated.
The strength of the semiconductor substrate remarkably drops near 1,000° C. at which a thermal oxidation step is carried out in comparison with a temperature near room temperature, and dislocation is extremely likely to occur. Accordingly, stress control is also very important.
In the ordinary thermal oxidation process, a thin thermal oxide film (which will be hereinafter referred to as a “pad oxide film”) is first formed on the semiconductor substrate surface so as to protect the semiconductor substrate from the internal stress of the silicon nitride film, and the silicon nitride film is then deposited. The value of the resolved shear stress occurring in the semiconductor substrate below the end portion of the silicon nitride film can be limited to be below the dislocation occurrence limit by controlling the film thickness of this pad oxide film, and the occurrence of dislocation can be thus prevented.
When the grooves are formed on the substrate surface to restrict the growth of the bird's beak, however, the stress field occurring near the substrate surface is likely to change, and the value of the resolved shear stress increases in accordance with the depth of the grooves formed.
FIGS. 2A and 2B
of the accompanying drawings illustrate an example of analysis of the relationship between the depth of the groove formed on the substrate surface and the resulting stress. The abscissa in
FIG. 2B
represents the groove depth (that is, an over-etch quantity D of the substrate) and the ordinate represents the maximum stress (that is, a maximum stress at the mask end).
Incidentally, the ordinate is normalized by a stress value before the formation of the groove. It can be understood that the resulting stress increases due to the formation of the groove. A stress concentration field has existed at only the end portion of the silicon nitride film before the formation of the groove, but when the groove is formed, it also takes place at the lower end portion of the groove formed, too. These two stress concentration fields interfere with each other and eventually increase the resolved shear stress component in the direction of the slip plane on the sidewalls of the groove.
In this instance, there is the case where the resulting stress exceeds the dislocation occurrence limit value with the formation of the groove even when the stress value before the formation of the groove is below the dislocation occurrence limit value. As will be later described, this stress increase has dependence on the pattern dimension. Accordingly, when the grooves are formed on the semiconductor substrate surface, an appropriate counter-measure must be taken lest the increased stress exceeds the dislocation occurrence limit value.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a device structure, or a groove formation method, which restricts the resulting stress below the dislocation occurrence limit value when the grooves are formed on the semiconductor substrate surface (particularly in the thermal oxidation process).
It is another object of the present invention to provide a semiconductor device structure, and fabrication and design methods thereof, which prevent the occurrence of crystal defects in the thermal oxidation process in a semiconductor production process.
Incidentally, the term “dislocation occurrence limit stress” means a limit value of the stress above which dislocation occurs in the silicon single crystal. The shear stress in the direction of the (
111
) slip plane of the silicon single crystal is used hereby as the stress, and is generally referred to as the “resolved shear stress”.
This stress value changes with a production method of a crystal, with an impurity concentration, with a temperature, and so forth. Therefore, a value corresponding to the material or temperature practically used must be employed.
To accomplish the objects described above, the present invention stipulates the structural dimension so that a ratio of the width of the device formation region to the width of the device isolation region adjacent to the device formation region keeps a predetermined value at which the resulting stress is below the dislocation occurrence limit value.
When the width dimension L, taken from 0.1 to 125 &mgr;m, of the device formation region is defined, the width dimension S, taken from 0.1 to 2.5 &mgr;m, of the device isolation regions so encompassing the device formation region as to correspond to a predetermined groove depth (in which the groove is formed in the device isolation area before the isolation oxide film is formed), is made sufficiently great so that the ratio L/S is below a predetermined value. When the minimum value of the S dimension is defined, the width dimension L of the device formation region adjacent to the device isolation regions is designed so that the ratio L/S is below the predetermined value, by reducing the size of the device formation region or dividing the device formation region.
The structural design can be made by executing stress analysis by using a finite element method, and the L or S dimension is stipulated so that the stress analysis (predicted) value is smaller than the dislocation occurrence limit stress.
Generally, a semiconductor device such as a memory device comprises a memory portion and a peripheral circuit portion as shown in FIG.
16
. In the memory portion, very small device formation regions having a size of about 1 &mgr;m and having the same shape are periodically arranged with the device isolation being interposed between them. In this memory portion, the values of L and S are not greater than about 1 &mgr;m in most cases.
In the peri

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