Patent
1986-11-04
1988-06-14
Sikes, William L.
G02B 612, G02B 610, H01L 2302, H01J 500
Patent
active
047508000
ABSTRACT:
An integrated optic IO device chip with anisotropic thermal expansion properties is packaged in a material enclosure by first bonding the chip to a substrate having anisotropic thermal expansion properties substantially equivalent to those of the IO device and substrate thickness substantially greater than that of the IO device, and bonding the substrate to the enclosure.
REFERENCES:
patent: 3874782 (1975-04-01), Schmidt
patent: 4400052 (1983-08-01), Alferness
patent: 4649624 (1987-03-01), Reedy
Fournier Joseph T.
Lopiccolo Mario T.
Swarts Richard E.
Chiantera Dominic J.
Sikes William L.
Ullah Akm E.
United Technologies Corporation
LandOfFree
Low stress mounting of integrated optic chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low stress mounting of integrated optic chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low stress mounting of integrated optic chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-501640