Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-04-30
2001-06-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C029S025010
Reexamination Certificate
active
06245583
ABSTRACT:
The present invention relates in general to the field of integrated circuit assembly and more specifically to methods of reducing mechanical stresses when semiconductor chips having dielectric layers of low dielectric constants are flip-chip assembled onto substrates.
BACKGROUND OF THE INVENTION
It is known to mount a semiconductor chip having an integrated circuit chip to a printed circuit substrate by solder bump interconnections. The integrated circuit on the semiconductor chip is spaced apart from the printed circuit substrate by a gap. The solder bump interconnections extend across the gap and connect contact pads on the integrated circuit chip to contact pads on the printed circuit substrate to attach the chip and then conduct electrical signals, power and ground potential to and from the chip for processing. There is a significant difference between the coefficient of thermal expansion (CTE) between the semiconductor material used for the chip and the material typically used for the substrate; for instance, with silicon as the semiconductor material and plastic FR-4 as substrate material, the difference in CTE is about an order of magnitude.
As a consequence of the CTE difference, mechanical stresses are created when the assembly is subjected to thermal cycling during use or testing. These stresses tend to fatigue the solder bump interconnections, resulting in cracks and thus eventual failure of the assembly. In order to strengthen the solder joints without affecting the electrical connection, the gap is customarily filled with a polymeric material which encapsulates the bumps and fills any space in the gap between the semiconductor chip and the substrate. For example, in the well-known “C-4” process developed by the International Business Machines Corporation, polymeric material is used to fill any space in the gap between the silicon chip and the ceramic substrate.
The encapsulant is typically applied after the solder bumps are reflowed to bond the integrated circuit chip to the printed circuit substrate. A polymeric precursor, sometimes referred to as the “underfill”, is dispensed onto the substrate adjacent to the chip and is pulled into the gap by capillary forces. The precursor is the heated, polymerized and “cured” to form the encapsulant. It is well known in the industry that the elevated temperature and the temperature cycling needed for this curing can also create mechanical stresses which can be detrimental to the chip and the solder interconnections. The stresses may delaminate the solder joint, crack the passivation of the chip, or propagate fractures into the circuit structures. In general, the sensitivity to cracking of the layered strucutres of integrated circuits is increasing strongly with decreasing thicknesses of the various layers.
Technical approaches have been proposed with the intent to reduce or mitigate the detrimental effects of the thermally induced stresses upon the assembly and thereby extend the useful life of the assembly. As an example, U.S. Pat. No. 5,720,100 of Feb. 24, 1998 (Skipor et al., “Assembly Having a Frame Embedded in a Polymeric Encapsulant and Method for Forming Same”) describes a method of embedding a frame made of ceramic or alumina in the polymeric precursor prior to curing such that the frame is disposed about the integrated circuit chip. During curing and later during thermal cycling, the frame provides enhanced mechanical strength by locally constraining the substrate and the encapsulant to reduce the effect of stresses, and the frame is affixed to the substrate so that the frame becomes an integral part of the substrate. The proposal is expensive and does not prevent the stresses to appear in the first place. Until now, there has been no known production-worthy solution to the problem of thermally induced stress and its deleterious effects on mechanically brittle insulator or metal-semiconductor structures.
In addition, there is presently a strong effort throughout the semiconductor industry to increase the speed of multi-level metallization integrated circuits by reducing the RC time constant, with preference of reducing the interlevel and intralevel capacitance C, rather than the resistance R. One way of reducing C is by developing insulator layers with materials or structures exhibiting low dielectric constants, with the additional benefit of minimiziong voltage induction, or cross talk, between adjacent signal lines (a requirement particularly important for digital signal processing devices).
One approach to fabricate thin layers of low dielectric constant has been described in U.S. Pat. No. 5,607,773 of Mar. 4, 1997 (Ahlburn et al., “Method of Forming a Multilevel Dielectric”). It teaches a method of depositing and curing layers alternating between plasma-generated tetraethylorthosilicate (TEOS) oxide and silicon-containing hydrogen silsesquioxane (HSQ). The dielectric constant of an HSQ film is lower than the dielectric constant of a plasma TEOS oxide or ozone TEOS oxide. Also, the density and porosity of the dielectric film affect the dielectric constant through absorption or desorption of water. Other efforts are studying the formation of thin layers of organic material or chemical vapor-deposited polymers. In all these endeavours (and even in hard oxides) experience has shown abundantly that decreasing film thickness causes dramatic increases in layer sensitivity to mechanical stresses. This trend is especially pronounced in large-area chips because the stress levels increase with increasing distance from the center of the chip. Thin layers easily develop cracks, and thus device failure, during attachment to customer circuit boards or during device operation and temperature cycling and testing.
Consequently, a need has arisen for an assembly material selection and method of fabrication that provide stress-free, simple and low-cost processes for chip-to-substrate assemblies, applicable to large-chip semiconductor products. At the same time, the method should be flexible to be applied to a wide spectrum of material and process variations, leading to improved semiconductor device reliability. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
The present invention comprises semiconductor ball-grid array packages, chip-size packages and flip-chip assemblies with improved mechanical reliability achieved by dramatically reduced stress during fabrication. The invention is particularly important for all semiconductor products employing thin insulating layers with low dielectric constants and high mechanical brittleness, often in a multi-level architecture. The invention defines the process rules for solder attachment and underfill and the methods for fabricating the chip/substrate assemblies without cracking the thin dielectric layers.
Semiconductor assemblies such as ball-grid array packages contain meterial with different coefficients of thermal expansion (CTE); they are coupled mechanically intimately, even rigidly to each other. Expressing CTE in ppm/° C., silicon has approximately 2.3, various metals from 4.3 to 17.0, and various plastics from 16.0 to 25.0. Consequently, whenever these assemblies undergo temperature excursions, the swings of increasing and decreasing temperatures induce different expansions and contractions in the materials couples to each other, causing tensile and compressive stresses to build up in the component parts. If the package were a uniform laminate structure, the stresses in each individual layer could be analytically modeled. However, the package is not a uniform laminate, and the variations from the uniform laminate case create stress concentrations. Further, the package is assembled through a series of thermal process steps which build in stresses between various layers. Finite element analysis and measurements by test structures have proven indispensable in quantifying these stresses and locating strain and stress maxima.
In known technology, these strain
Amador Gonzalo
Hotchkiss Gregory B.
Honeycutt Gary C.
Navarro Arthur I.
Niebling John F.
Stevenson Andre′ C
Telecky Fred
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