Low stress flip-chip package for low-K silicon technology

Details Low stress flip-chip package for low-K silicon technology Low stress flip-chip package for low-K silicon technology

2007-03-13

2007-03-13

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

With specified filler material

C257S787000, C257S778000, C257S737000, C257SE23121, C257S789000

Reexamination Certificate

active

10396955

ABSTRACT:
An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.

REFERENCES:
patent: 6251705 (2001-06-01), Degani et al.
patent: 6335571 (2002-01-01), Capote et al.
patent: 6724091 (2004-04-01), Jayaraman et al.
patent: 2002/0031868 (2002-03-01), Capote et al.
patent: 2004/0086719 (2004-05-01), Chan et al.

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