Low stress cavity package

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame

Reexamination Certificate

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Details

C257SE21510, C257SE23037, C438S123000

Reexamination Certificate

active

07868433

ABSTRACT:
The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity.

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U.S. Appl. No. 11/048,309, filed Jan. 31, 2005.
U.S. Appl. No. 10/953,002, filed Sep. 28, 2004.
U.S. Appl. No. 11/836,662, filed Aug. 9, 2007.
U.S. Appl. No. 10/969,729, filed Oct. 19, 2004.

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