Metal fusion bonding – Process – With disassembling of bonded joint
Reexamination Certificate
2002-09-03
2004-06-08
Stoner, Kiley (Department: 1725)
Metal fusion bonding
Process
With disassembling of bonded joint
C228S013000, C228S264000
Reexamination Certificate
active
06745932
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacture and test of electronic devices, and more particularly, to the removal of a chip from an electronic test module without damaging the chip or the attached solder balls.
2. Description of the Related Art
High performance chips (or dies) with increased logic complexity require advanced testing before they are assembled into final products. Further, the increased operating frequency of these advanced chips impose severe constraints to the electronic test processes and requires testing to be carried out under environmental conditions as close as possible to the conditions which the final product will endure in the field.
Conventional state of the art electronic testing uses temporary electronic packages that allow all of the input/output connectors to be simultaneously available for electronic testing. The need for simultaneous testing increases significantly as the number of advanced chips needed to assemble the final product increases.
The need to reduce production costs and continuously scale down chip features and scale up solder ball count and/or chip size has led to the use of electroplating processes as an efficient method to fabricate the chip solder balls needed for electrical interconnection to a temporary electronic test package. To avoid excessive chip (die) processing and handling during and after die testing, the chips must be separated from the temporary electronic testing package without damaging the die solder balls. Conventional separating processes use a spring loaded plunger which shears the chip from the module in a direction parallel to the chip surface to separate the die from the temporary electronic test package. To improve process repeatability, the spring force is adjusted each time with the help of a load gauge that uses a nominal sample size as dimensional reference.
However, if just one solder ball detaches at the wrong side (i.e., at the chip side) during separation, even without damaging the chip surface, the chip is deemed useless, i.e., because each damaged interconnect must be repaired and conventional repair processes are too time consuming, too expensive, and/or do not satisfy current quality control specifications.
Each conventional testing procedure comprises a module yield that reflects the percent of chips which are successfully detached (i.e., detached at the package side). Advanced chip testing requires 100% module yield. However, conventional separation techniques cannot consistently produce 100% module yield.
Conventional chip detach methods such as those disclosed in U.S. Pat. No. 5,553,766, entitled “In-situ Device Removal For Multi-chip Modules,” and U.S. Pat. No. 6,216,937, entitled “Process And Apparatus To Remove Closely Spaced Chips On A Multi-chip Module,” teach the use of bimetallic disk or memory device to pull the chip from a package once the assembly reaches solder softening point or, in other words, gripping and pulling the chip at different operating temperatures relative to the solder ball melting points. However, these detach techniques cannot guarantee that the solder balls will stay on the chip after chip detachment.
A conventional chip detach technique which offers more control (i.e., that the solder balls will say on the chip after chip detachment) involves shearing the chip from the package. To facilitate the solder ball separation at the package interface instead of at the chip interface, the temporary connection point in the package is built with smaller contact area than the solder ball base on the chip side. The temporary module is detached after electronic testing using a standard continuous belt furnace which heats the module and shearing hardware to a temperature near but not exceeding the solder ball melting point.
This process works well with packages with large solder balls and low solder ball count, such as packages with solder balls larger than 4.7 mil. in diameter and solder ball counts of less than 2000, mainly because the total force required to successfully shear the chip is low and the process window is large. The process window is the difference in the amount of force needed to separate each solder ball of a given chip at the package side from the amount of force needed to separate at least one solder ball from the chip side.
Unfortunately, this process is difficult to control when the chip has a large number of solder balls and/or with smaller size solder balls. A larger number of solder balls increases the total force needed to separate the chip with the consequent increase in the total force distribution range seen by the solder ball population in a given chip. Smaller solder balls reduce the solder ball base on the chip, thus reducing the range separating the shearing forces needed to shear the solder ball at the chip-package interface relative to the force needed to shear the solder ball at the chip interface. In addition, a larger number of solder balls also requires a larger die.
SUMMARY OF THE INVENTION
In view of the limitations of the conventional chip detach processes, the present invention provides a chip detach apparatus and method that limits the solder ball maximum shear rate and, more particularly, delays the application of shear force until a minimum predefined temperature is reached. In addition to being applicable to chips in general, the chip detach apparatus and method is specifically applicable to chips with high solder ball counts, chips with small solder ball sizes, and chips with weak surface strength. Furthermore, the chip detach apparatus and method measures and accounts for variability in the electronic module manufacturing and assembly.
REFERENCES:
patent: 3748719 (1973-07-01), Fuller et al.
patent: 3800996 (1974-04-01), Fuller et al.
patent: 4202482 (1980-05-01), Sade et al.
patent: 4561584 (1985-12-01), Hug
patent: 4561586 (1985-12-01), Abel et al.
patent: 4696096 (1987-09-01), Green et al.
patent: 4899920 (1990-02-01), Abbagnaro et al.
patent: 4972990 (1990-11-01), Abbagnaro et al.
patent: 5081739 (1992-01-01), Kao
patent: 5553766 (1996-09-01), Jackson et al.
patent: 5620132 (1997-04-01), Downing et al.
patent: 5779133 (1998-07-01), Jackson et al.
patent: 5868297 (1999-02-01), Zabel et al.
patent: 6053393 (2000-04-01), Burke et al.
patent: 6131794 (2000-10-01), Burke et al.
patent: 6216937 (2001-04-01), DeLaurentis et al.
patent: 6360938 (2002-03-01), DeLaurentis et al.
patent: 6360940 (2002-03-01), Bolde et al.
patent: 6528352 (2003-03-01), Jackson et al.
U.S. 2002/0088846A1 Bolde (Jul. 11, 2002).
Bezama Raschid J.
Natarajan Govindarajan
Pasco Robert W.
International Business Machines Corp.
McGinn & Gibb PLLC
LandOfFree
Low strain chip removal apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low strain chip removal apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low strain chip removal apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3363293