Low spurious charge pump

Details Low spurious charge pump Low spurious charge pump

2005-04-26

2005-04-26

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S008000, C327S111000, C327S112000, C327S382000, C327S157000

Reexamination Certificate

active

06885251

ABSTRACT:
Phase locked loop charge pump comprising a drain node (A, B) and at least a cascode transistor (M4, M6) for limiting the variation of the voltage of said drain node, characterized in that an intermediate switch transistor (M3, M5) is placed between the drain node (A, B) and the cascode transistor (M4, M6).

REFERENCES:
patent: 5825640 (1998-10-01), Quigley et al.
patent: 6052015 (2000-04-01), Desbonnets
patent: 6160432 (2000-12-01), Rhee et al.
patent: 6320435 (2001-11-01), Tanimoto
patent: 6415007 (2002-07-01), Kawasumi
Patent Abstracts of Japan, May 31, 1999, vol. 1999, No 05 & JP 11 046138 A (Sharp Corp), Feb. 16, 1999.
Patent Abstracts of Japan, Jul. 31, 1997, vol. 1997, No. 07, & JP 09 074739 A (NEC Corp.),Mar. 18, 1997.
Lin Li, et al., “A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer Using a Wideband PLL Architecture”, 2000 IEEE International Solid State Circuits Conference, 2000.

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