Low speed access to DRAM

Pulse or digital communications – Cable systems and components

Reexamination Certificate

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Details

C375S219000, C375S220000, C375S222000, C702S117000, C711S167000

Reexamination Certificate

active

07580465

ABSTRACT:
Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

REFERENCES:
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6996749 (2006-02-01), Bains et al.
patent: 2005/0080581 (2005-04-01), Zimmerman et al.
U.S. Appl. No. 11/238,897, filed Sep. 28, 2005, Zimmerman.

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