Low speed access to DRAM

Details Low speed access to DRAM Low speed access to DRAM

2005-06-30

2009-08-25

Phu, Phuong (Department: 2611)

Pulse or digital communications

Cable systems and components

C375S219000, C375S220000, C375S222000, C702S117000, C711S167000

Reexamination Certificate

active

07580465

ABSTRACT:
Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

REFERENCES:
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6996749 (2006-02-01), Bains et al.
patent: 2005/0080581 (2005-04-01), Zimmerman et al.
U.S. Appl. No. 11/238,897, filed Sep. 28, 2005, Zimmerman.

Affiliated with

Also associated with

Rating

Low speed access to DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low speed access to DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low speed access to DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4133305