Low skew system for interfacing asics by routing internal clock

Details Low skew system for interfacing asics by routing internal clock Low skew system for interfacing asics by routing internal clock

1994-01-27

1995-05-16

Lee, Thomas C.

Boots, shoes, and leggings

364270, 3642715, 364DIG1, G06F 104, G06F 110

Patent

active

054169186

ABSTRACT:
A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.

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Itoh et al., "A Novel Design Concept for Small Skew Clock LSI with the Self-Delay-Adjustment ", IEEE 1991 Bipolar Circuits & Technology Meeting, pp. 130-133.
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