Low skew minimized clock splitter

Details Low skew minimized clock splitter Low skew minimized clock splitter

2001-03-30

2002-10-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S256000, C327S257000, C327S259000, C327S293000, C326S082000, C326S085000, C326S087000

Reexamination Certificate

active

06466074

ABSTRACT:

FIELD
The present invention is directed to a clock generator for producing two clock signals 180° out of phase. More particularly, the present invention is directed to a clock splitter which produces multiple clock signals at different phases having low skew between them where the generators are made of PMOS and NMOS transistors.
BACKGROUND
Many high speed signaling components in electronic devices utilize a fast clock frequency. In such devices, it is often necessary to have clock signals having different phases but the same frequency. Often, the different clock signals are generated from the same original clock signal but with one inverted or otherwise phase delayed to obtain the necessary phase difference. While such a simple approach produces a suitable set of clock signals for many purposes, it is desirable to obtain clock signals having less skew for high speed signaling devices.
Skew in this case is defined as being a measure of the difference in the rising and falling edges of the output clock signals from that which is desired. In particular, if the clock signals are designed to be 180° out of phase, the rising edge of one should be at the same time as the falling edge of the other. Thus, skew is the measure of how far out of alignment the two signals are relative to each other.
One type of disadvantageous arrangement is shown in FIG.
1
. In this arrangement of a loaded inverter chain, an input clock signal is applied to two different paths of inverters, one of which has an odd number of inversions and the other an even number. Thus, one of the output signals will be 180° out of phase with the other due to the extra inversion. Capacitive loads
12
are added to the inverter outputs and are adjusted so that the total delay of the inverting path matches the total delay of the non-inverting path. While these two paths can be adjusted in this manner to have an equal delay for a given set of parameters such as voltage, temperature and process, these path delays will vary under other parameters. This is because the load delay was adjusted to equal the propagation delay through an inverter but the inverter delay will vary differently than the wire or load delay for different process corners. Accordingly, while this arrangement can be suitable for some purposes, it does not produce a stable low skew clock signal arrangement.
Another arrangement is shown in FIG.
2
A and is known as an exclusive NOR pair. In this arrangement the clock signal forms one input to each of two gates. The other input to one gate is connected to a high voltage (VCC) while the other input of the other gate is connected to a low voltage (VSS). Thus, since one input is always high or always low, outputs are obtained in opposite directions from the two gates. An alternative arrangement has these gates being exclusive OR gates.
FIG. 2B
shows a exclusive NOR arrangement for one of the gates in FIG.
2
A. In this arrangement, A is the equivalent of the “a” input of
FIG. 2A
, which is connected either to the high or low voltage source. The B input is the same as the “b” input which is connected to the input clock signal. The CO output is the same as the output “o” from the logic gates. It is clear that the actual circuitry needed for the logic gate is reasonably complex and a number of transistors must be used in order to make such a gate. More importantly, because of the complexity of the device, it is difficult to balance the output to a high degree so that the skew between the two clock signals is minimized. Such a logic tree shown in
FIG. 2B
would be unbalanced with the A and B input devices being in series. A typical remedy is to add complementary series trees as shown in FIG.
2
A. Delay differences due to the A-input N-channel device being above the B-input P-channel device would be complementary compensated by the second series stack with the B input, N-channel device on top. The corresponding A and B P-channel devices are already in parallel. Unfortunately, the inversion created by transistors
20
and
22
is not complementary compensated and thus a delayed mismatch occurs between the two paths. Trying to compensate for this inversion creates an even more complex situation and more sensitivity to varying parameters.
Thus, it is clear that these disadvantageous arrangements have limitations.


REFERENCES:
patent: 4456837 (1984-06-01), Schade, Jr.
patent: 4785203 (1988-11-01), Nakamura
patent: 4890016 (1989-12-01), Tamaka et al.
patent: 4987324 (1991-01-01), Wong et al.
patent: 5047659 (1991-09-01), Ullrich
patent: 5149990 (1992-09-01), Yamazaki et al.
patent: 5568081 (1996-10-01), Lui et al.

Affiliated with

Also associated with

Rating

Low skew minimized clock splitter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low skew minimized clock splitter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low skew minimized clock splitter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2997792