Low skew differential receiver with disable feature

Details Low skew differential receiver with disable feature Low skew differential receiver with disable feature

1999-03-24

2000-02-15

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800, G11C 700

Patent

active

060260513

ABSTRACT:
A differential clock receiver for a SynchLink-type Synchronous Dynamic Random Access Memory (SLDRAM) includes a differential amplifier with a novel method for biasing its NMOS and PMOS current sources. A differential clock received and amplified by the differential amplifier switches a set of multiplexers, which respond by outputting a differential output clock. The multiplexers can be "disabled" by an inactive enable signal so they output a constant "0" level for the differential output clock. This disabling feature of the differential clock recciver is particularly useful with the intermittent data clocks found in SLDRAMs. Also, the novel biasing method for the current sources of the differential amplifier gives the clock receiver very low skew.

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