Low skew CMOS clock divider

Details Low skew CMOS clock divider Low skew CMOS clock divider

1992-06-30

1993-09-28

Sikes, William L.

Electrical pulse counters, pulse dividers, or shift registers: c

Pulse counting or dividing chains

Using bistable regenerative trigger circuits

377 47, 377 48, 377118, H03K 2136

Patent

active

052492141

ABSTRACT:
A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.

REFERENCES:
patent: 4545063 (1985-10-01), Kamimaru
patent: 4575867 (1986-03-01), Hogue
patent: 4669099 (1987-05-01), Zinn
patent: 4759043 (1988-07-01), Lewis

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