Low skew clock input buffer and method

Details Low skew clock input buffer and method Low skew clock input buffer and method

2005-01-25

2005-01-25

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C326S093000, C326S098000, C327S291000, C327S295000

Reexamination Certificate

active

06847582

ABSTRACT:
An input buffer includes first and second cross-coupled differential amplifiers. Each amplifier drives a buffer signal from a first logic state to a second logic state at a first slew rate when input signal transitions from a first logic state to a second logic state and a complementary input signal transitions from the second logic state to the first logic state, and drives the buffer signal from the second logic state to the first logic state at a second slew rate when the signal transitions are the complement of these previous transitions. An output circuit generates a first edge of an output signal when the buffer signal from the first amplifier transitions from the first logic state to the second logic state and generates a second edged of the output signal when the buffer signal from the second amplifier transitions from the first to the second logic state.

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