Low roundoff noise digital filter

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364745, G06F 1531

Patent

active

042362245

ABSTRACT:
An error feedback circuit is employed in a digital filter to significantly lower noise in the output by feeding back the least significant (roundoff) output bits of the quantizer rather than throwing these bits away as is done in the prior art. The feedback circuit for accomplishing this end result includes a digital delay circuit which receives the roundoff bits and delays these bits for a sampling sequence (Z.sup.-1) (as is also done for the rounded bits), a multiplier which multiplies the output of the delay circuit by a predetermined integer and an adder which subtracts the output of the multiplier from the delayed filtered digital output signal which has been multiplied by a predetermined constant.

REFERENCES:
patent: 3749895 (1973-07-01), Kao
patent: 3906199 (1975-09-01), Kieburtz et al.
patent: 3997770 (1976-12-01), Claasen et al.
patent: 4034196 (1977-07-01), Butterweck et al.
Parker et al. "Limit-Cycle Oscillations in Digital Filters", IEEE Trans. on Circuit Theory, vol. CT-18, No. 6, Nov. 1971, pp. 687-697.

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