Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-02-12
2003-04-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S112000, C438S113000, C438S612000
Reexamination Certificate
active
06541301
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the fabrication of integrated circuits, and more particularly to a method and apparatus which uses through-wafer via holes for both signal connections and ground connections within a semiconductor device, and wherein the device is attached to a circuit board using selectively placed conductive epoxy or solder attachment.
BACKGROUND OF THE INVENTION
It is well known in the art of integrated circuit (IC) processing and fabrication that bond pads for signal connections are placed around the perimeter of ICs, while through-wafer via holes are utilized for ground connections. It has been determined that for high frequency (e.g. X-band) applications, one obtains higher performance if the grounds are placed at locations closer to where they are utilized, rather than on the sides of the chips. In the prior art as shown in
FIG. 3
, these via holes
50
are used as ground connections between the active elements placed on the top surface
60
a
of a substrate (chip)
60
of an IC chip, and the bottom surface or backside
60
b
of the substrate
60
. A metallized layer
70
(typically of solder) is formed on the backside
60
b
to provide the ground connection. In the prior art, the entire backside
60
b
of the substrate
60
is metallized to provide the ground connection of circuit board
90
with the top surface
60
a
of the substrate
60
by means of the via holes
50
. Wire bonds
55
are then connected to the active elements of the chip
60
by coupling to bond pads
57
located around the perimeter of the chip
60
to provide positive and/or negative signal connections with electrodes
59
a
,
59
b
of the circuit board
90
. Such signal connections are used in the fabrication of power amplifiers and other electronic devices utilizing positive and negative voltages, RF input and output signals, and the like. A heat sink or shim
66
is generally provided between the circuit board
90
and the IC chip
60
to perform the task of spreading and dissipating the heat buildup.
A number of problems, however, exist with the attach process and semiconductor apparatus described above in conjunction with FIG.
3
. First, the use of the wire bonds for connecting with the bond pads around the perimeter of an IC chip poses a number of problems in the fabrication and operation of these electronic devices. For example, the length of the wire bond provides a source of variation which effects matching. Furthermore, the loop in the wire emits stray RF signals which result in signal loss and increased crosstalk. Accordingly, it is highly desirable to obtain a process and apparatus which eliminates these wire bonds and which allows signal connections in addition to ground connections to be provided at a position much closer to the active elements on the top surface of the substrate.
The present invention achieves this advantage through the use of through-wafer via holes for both signal and ground connections and provides a low RF loss semiconductor wafer die wherein patterned metalized layers are formed within a plurality of via holes on a semiconductor substrate and where an electronic member, such as a circuit board, is attached to the die using selectively placed conductive epoxy or solder attach. This permits RF signals to be fed in and out through the backside vias, in addition to ground connections, thereby eliminating the need for wire bonds.
SUMMARY OF THE INVENTION
A method for electronically connecting a semiconductor device comprising a substrate having a backside surface and a top surface on which is formed active elements, to an electronic circuit board having at least two electrical contacts connected to sources of different potentials for communicating at least two different signals; the method comprising forming at least two through-wafer via holes on the backside surface of the semiconductor substrate beneath each of the active regions extending therethrough to the top surface; forming a conductive layer of material within each of the via holes extending therethrough, each of the conductive layers formed within the corresponding via holes being electrically separated from one another; the at least two electrical contacts on the circuit board congruently aligned with corresponding conductive layers and associated via holes; and attaching the circuit board to the semiconductor substrate at each of the corresponding electrical contacts and conductive layers so as to provide electrical communication of the first signal with one of the active elements on the substrate through at least one of the via holes and to provide electrical communication of the second signal with one of the active elements on the substrate through at least another one of the via holes.
There is also provided a composite semiconductor device comprising an integrated circuit in electrical communication with a circuit board, the integrated circuit comprising: a semiconductor wafer substrate having a top surface on which active elements are formed, and a backside surface, a plurality of through wafer via holes formed on the backside surface, a plurality of conductive layers, each conductive layer disposed in a corresponding one of the via holes and electrically separated from one another; the circuit board having a plurality of electrodes for communicating various signals, wherein at least two of the electrodes are connected to sources of different potential on the circuit board, whereby the at least two electrodes communicate signals of different potential, the at least two electrodes congruently aligned with and in electrical communication with corresponding conductive layers each associated with one of the via holes in the semiconductor wafer so as to communicate the at least two signals of different potential between the semiconductor top surface and the circuit board electrodes through separate via holes.
REFERENCES:
patent: 4631812 (1986-12-01), Young
patent: 4694570 (1987-09-01), Rudolph et al.
patent: 5044069 (1991-09-01), Asai et al.
patent: 5455064 (1995-10-01), Chou et al.
patent: 5692292 (1997-12-01), Asai et al.
patent: 6107119 (2000-08-01), Farnworth et al.
Fuji America Corporation; CP-642 High Speed Chip Placer; 1998; pp. 1-3.
Fuji America Corporation; CP-43 High Speed Chip Placer; 1998; pp. 1-3.
Anya Igwe U.
Duane Morris & Heckscher LLP
Plevy, Esq. Arthur L.
Smith Matthew
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