Low resistivity titanium silicide on heavily doped...

Details Low resistivity titanium silicide on heavily doped... Low resistivity titanium silicide on heavily doped...

2006-12-12

2006-12-12

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S764000, C257S770000

Reexamination Certificate

active

07148570

ABSTRACT:
Low resistivity, C54-phase TiSi2is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi2, forming a low-resistivity, C54-phase TiSi2film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi2is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (<0.3 μm) of low-resistivity, C54-phase TiSi2films on heavily doped polysilicon are thus achieved.

REFERENCES:
patent: 5164333 (1992-11-01), Schwalke et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6488776 (2002-12-01), Wang
patent: 2002/0045342 (2002-04-01), Hu et al.
Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey, (1993), pp. 44-50.
T. Nakayama, T. Asamura, M. Kako, M. Murota, M. Matsumoto, Y. Washizu, K. Tomose, K. Kasai, Y. Okayama, K. Hashimoto, K. Ohuchi, K. Hattori, J. Shiozawa, H. Harakawa, F. Matsuoka, and M. Kinugawa, “Excellent Process Control Technology for Highly Manufacturable and High Performance 0.18 um CMOS LSIs” IEEE Digest Tech. Papers, Symposium on VLSI Technology, (1998) pp. 146-147.
A. S. Spinelli, A. Pacelli, and A. L. Lacaita, “An Improved Formula for the Determination of the Polysilicon Doping,” IEEE Electron Device Letters, vol. 22, No. 6, (Jun. 2001) pp. 281-283.
Masaki Tsukude, Takahisa Eimori, and Kazutami Arimoto, “A 256 Mb DRAM,” Advance Magazine, Mitsubishi Electric, vol. 75, (Jun. 1996), pp. 5-8.
S. P. Murarka, Silicides for VLSI Applications (Academic, Orlando, 1983).
L. A. Clevenger, R.W. Mann, R. A. Roy, K. L. Saenger, C. Cabral, and J. Piccirillo, J. Appl. Phys. 76, 7874 (1994).
C. A. Sukow and R. J. Nemanich, J. Mat. Res. 9, 1214 (1994).
I. Sakai, H. Abiko, H. Kawaguchi, T. Hirayama, L.E.G. Johansson, and K. Okabe: Symp. VLSI Technol. Dig, 66 (1992).

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