Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-07-02
2002-01-15
Clark, Jhihan B. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S758000
Reexamination Certificate
active
06339258
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an alpha-phase tantalum exhibiting relatively low resistivity and a high degree of orientation and a method for fabricating the alpha-phase tantalum. In addition, the alpha-phase tantalum according to the present invention is especially useful as a barrier layer and particularly in copper chip interconnection structures. Furthermore, the alpha-phase tantalum acts as a redundant current layer in such structures and finds use in chip structures, packaging, flat panel displays and in magnetics.
BACKGROUND OF INVENTION
Aluminum and its related alloy, AlCu, are currently the predominantly used conductors for forming interconnection from electronic devices such as integrated circuits. The amount of Cu in AlCu is typically in the range of about 0.3 to about 4%.
Replacement of AlCu by Cu and Cu alloys as a chip interconnection material results in advantages of improved chip performance. Performance is improved because the resistivity of Cu and in certain copper alloys is less than the resistivity of AlCu. Besides performance, high chip yield count and higher circuit wiring densities are also realized.
In addition, interest in using copper as interconnects in semiconductor devices has increased since it possesses a reduced susceptibility to electromigration failure as compared to the more traditional aluminum or aluminum alloy interconnects.
The advantages of copper metallization have been recognized by the entire semiconductor industry. Copper metallization has been the subject of extensive research documented by two entire issues of the
Materials Research Society
(
MRS
) Bulletin. One dedicated to academic research on the subject is
MRS Bulletin
, Vol. XVIII, No. 6 (June 1993) and the other dedicated to industrial research in
MRS Bulletin
, Vol. XIX, No. 8 (August 1994). A 1993 paper by Luther et al, “Planar Copper-Polyamide Back End of the Line Interconnection for ULSI Devices”, in
Proc. IEEE VLSI Multilevel Interconnections Conference
, Santa Clara, Calif., Jun. 8-9, 1993, p. 15, describes the fabrication of copper chip interconnections with four levels of metallization.
However, since copper has a tendency when used in interconnect metallurgy to diffuse into surrounding dielectric materials such as silicon dioxide, encapsulation of the copper is essential. The capping inhibits this diffusion. One widely suggested method of capping includes employing a conductive barrier layer along the sidewalls and bottom surface of a copper interconnect. Typical of such barrier layers is tantalum and titanium, and nitrides thereof. Capping of the upper surface of a copper interconnect usually employs silicon nitride.
The tantalum employed is typically an alpha-phase tantalum layer, which besides acting as a barrier, also acts as a redundant current carrier layer to assist the main conductor copper in current distribution. Moreover, it becomes the main conductor in the event the copper fails due to electromigration. However, the resistivity of the presently available alpha-phase tantalum layer is typically about 25 micro ohm-cm. Although this resistivity is adequate, it leaves room for improvement. Accordingly, it would be desirable to reduce the resistivity of the redundant conducting layer to be as low as practical.
SUMMARY OF INVENTION
The present invention relates to a tantalum layer having significantly reduced resistivity. In addition, the tantalum layer according to the present invention has a high degree of orientation. More particularly, the present invention relates to an alpha-phase tantalum having a resistivity of about 15 micro-ohm-cm or lower.
The present invention also relates to a process for preparing the tantalum of the present invention. In particular, the process involves sputter deposition of tantalum employing a vacuum of at least about 1×10 E6 torr, power of about 0.5 to about 6 kilowatts, in the presence of an inert gas to provide an effective pressure of about 1 to about 10 millitorr.
The present invention also relates to an interconnection structure for semiconductor integrated circuits which comprises a layer of copper or copper alloy and a barrier layer of alpha-phase tantalum having a resistivity of about 15 micro-ohm-cm or less.
A further aspect of the present invention relates to an alpha-phase tantalum obtained by the above described process.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5447887 (1995-09-01), Filipiak et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5506449 (1996-04-01), Nakano et al.
patent: 5614437 (1997-03-01), Choudhury
patent: 5665628 (1997-09-01), Summerfelt
patent: 5668411 (1997-09-01), Hong et al.
patent: 5679980 (1997-10-01), Summerfelt
patent: 5686760 (1997-11-01), Miyakawa
patent: 5696018 (1997-12-01), Summerfelt et al.
patent: 6110598 (2000-08-01), Maeda et al.
patent: 0 751 566 (1997-02-01), None
patent: 55-132056 (1980-10-01), None
patent: 63-156341 (1988-06-01), None
patent: 6-275-622 (1994-09-01), None
patent: 6-310509 (1994-11-01), None
patent: 6-318591 (1994-11-01), None
patent: 11-340228 (1999-12-01), None
Luther et al, Planar Copper-Polyimide Back End of the Line Interconnections for ULSI Devices, VMIC Conference, Jun. 8-9, 1993, 15-21.
Method of Eliminating Ta Hydride Formation During Cu Plating on Ta Films, IBM TDB, vol. 34, No. 7A, Dec. 1991, 284.
Cooney, III Edward Crandal
Uzoh Cyprian Emeka
Abate Joseph P.
Clark Jhihan B.
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