Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-05-23
2003-02-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S057000, C257S059000, C257S383000, C257S384000, C257S408000, C257S751000
Reexamination Certificate
active
06525342
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to display devices, and more particularly to liquid crystal displays having additional wiring formed in a periphery region outside of the pixel array of the display. The additional wiring may be employed for a plurality of applications, such as driver chip wiring on the array, connecting gate metal to signal (or data) metal, etc. A simple, low cost fabrication method is disclosed.
2. Description of the Related Art
Active matrix displays typically include a pixel array, which includes a plurality of pixels arranged to form a matrix. A region surrounding the pixel array is often referred to as the periphery region. The periphery region includes support circuitry or connections to chips or other devices which provide power and addressing signals to the array of pixels.
For active matrix liquid crystal displays (AMLCDs), it is desirable to have low resistance wiring in the periphery region where the driver chips are attached so that an additional external circuit board is not needed to provide power and data signals to the driver chips if the chips are mounted directly on the glass (chip on glass (COG)). An additional low resistance wiring level and low resistance connections between the existing wiring levels (such as gate metal and data (or signal) metal) is desirable when additional functions, such as next generation array test (see, e.g., M. Kodate et al, “Next generation TFT array testing for high resolution high content AMLCDs”, SID '99 Digest, pp. 72-75), or integrated drivers are employed (see, e.g., F. P. Cuomo et al, “Sub-notebook a-Si color SVGA display with integrated drivers”, SID '98 Digest, pp. 967-970).
Current amorphous Si AMLCD manufacturing processes typically use 4 or 5 photolithography mask levels to make the TFT array, (see H. Kitahara, E. G. Colgan, and K. Schleupen, “Technology Trend of Large Size and High Resolution Direct View TFT-LCD”, SID '00 Digest, pp. 1108-1111 and C. W. Kim, Y. B. Park, H. S. Kong, D. G. Kim, S. J. Kang, J. W. Jang, and S. S. Kim, “A Novel Four Mask Count Process Architecture for TFT LCDs” SID '00 Digest, pp. 1006-1009). In these processes, and many other low mask count processes, the transparent pixel electrode is the final conductor patterned and is used to interconnect between the gate metal and data metal, if such connections are needed.
For large size, high resolution displays, a planarizing polymer layer is used underneath the pixel electrode so that the aperture ratio of the display can be increased, as in T. Ueki, “Requirements for Large Size and High Resolution TFT-LCDs”, IDMC '00 Digest, page 177-180. For a first level of metal (either gate metal or data metal) on a thin film transistor (TFT) array, the thickness is limited to about 300 nm because the lines fabricated from a second level of metal (either data or gate metal) must cross-over the first level lines numerous times with no shorts. The thickness of the second layer of metal is limited to about 400 nm if a planarizing polymer layer is not used since a passivation layer must fully cover the second metal layer in the array region.
A typical low resistance material used for gate and data metal is Al(Nd) (see e.g., H. Takatsuji, et al., “Nanometer scale investigation of Al based alloy films for thin film transistor liquid crystal display arrays,” Mat. Res. Soc. Symp. Proc. Vol. 471, pp. 99-104, 1997) which has a resistivity of about 3.5 microOhm-cm. This corresponds to 0.12 Ohm/square with a thickness of 300 nm and 0.09 Ohm/square with a thickness of 400 nm. Even with these layers stacked (resulting in a sheet resistance of about 0.05 Ohm/square), this is not low enough resistance for some of the desired applications.
Additionally, a practical layout frequently needs low resistance connections between gate metal and data metal which are presently connected through a high resistance transparent pixel electrode material (typically, Indium Tin Oxide, ITO, with a sheet resistance of about 50 Ohms/square). It is also undesirable to add an additional photolithography (mask) step to pattern an additional metal layer because of the high cost.
Therefore, a need exists for an additional low resistance wiring level and a method for fabrication which also provides connections between gate metal and data metal without additional photolithography steps. A further need exists for low resistance wiring in a periphery region of a display which does not impact pixel operation.
SUMMARY OF THE INVENTION
A display device and method for fabrication are disclosed. A gate metal and a data metal are formed in an array region and in a periphery region outside of the array region of the display device. A planarizing layer is formed over the array region and the periphery region, and vias are patterned into the planarizing layer in the array region and the periphery region to expose portions of at least one of the gate metal and the data metal. A transparent conductor is deposited in the array region and the periphery region.
A metal layer is locally deposited over the transparent conductor in selected areas of the periphery region. Then, using a same lithographic pattern, the metal layer and the transparent conductor are patterned to form an additional low resistance wiring level and connections between the gate metal and the data metal in the periphery region and to form pixel electrodes in the array region.
Another display device includes an array region including pixel cells, the pixel cells including metal lines. A periphery region is disposed outside of the array region, the periphery region including the metal lines which extend from the array region. A wiring layer is formed on the metal lines in the periphery region, the wiring layer including a layered stack. The stack includes a transparent conductor layer and an opaque metal layer.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 6252247 (2001-06-01), Sakata et al.
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patent: 6369410 (2002-04-01), Yamazaki et al.
patent: 6380558 (2002-04-01), Yamazaki et al.
Ueki, T.,Requirements for Large Size and High Resolution TFT-LCDs, International Display Manufacturers Conference, 2000 Digest, pp. 177-180.
Takatsuji, H., et al.,Nanometer-Scale Investigation of AL-Based Alloy Films for Thin-Film Transistor Liquid Crystal Display Arrays, Materials Research Society Symposium Proceedings, vol. 471, 1997, pp. 99-105.
Herman, H. et al.,Thermal Spray: Current Status and Future Trends, MRS Bulletin, Jul. 2000, pp. 17-25.
Takatsuji, H., et al.,Characterization of Transparent Conductors in Indium Zinc Oxide and their Application to Thin-Film-Transistor Liquid-Crystal Displays, Materials Research Society Symposium Proceedings, vol. 508, pp. 315-320.
Libsch, F.R., et al.,Invited Paper: Next Generation TFT-Array Testing for High-Resolution/HighContent AMLCDs, SID 99 Digest, , pp. 72-75.
Cuomo, F.P., et al.Sub-Notebook a-Si Color SVGA Display with Integrated Drivers, SID 98 Digest, pp. 967-970.
Kitahara, Hiroaki,Invited Paper: Technology Trend of Large Size and High Resolution Direct-View TFT-LCD, SID 00 Digest, pp. 1108-1111.
Kim, C.W., et al.,A Novel Four-Mask-Count Process Architecture for TFT-LCDs, SID 00 Digest, pp. 1006-1009.
Amemiya Takahisa
Arai Toshiaki
Colgan Evan George
Sakaguchi Yoshitami
Sakai Kazumi
F.Chau & Associates, LLP
Tran Mai-Houng
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