Low-resistance, fine-line semiconductor device and the method fo

Details Low-resistance, fine-line semiconductor device and the method fo Low-resistance, fine-line semiconductor device and the method fo

1978-11-13

1980-07-22

Mack, John H.

Chemistry: electrical and wave energy

Processes and products

Vacuum arc discharge coating

427 84, 427 89, 427 91, 29578, 29579, 29591, 430312, H01L 21441

Patent

active

042138400

ABSTRACT:
A method of fabricating gate electrodes on microwave field effect transistors is described. A first layer of photo-resist is deposited and photolithographically defined on top of a semiconductor material with openings in the photoresist, corresponding to the gate electrode. In one embodiment, when drain and source electrodes have been previously formed, additional openings in the first layer of photoresist are defined that approximately overlay the drain and source electrodes. A metal layer is then deposited on top of this structure. A second layer of photoresist is then deposited and photolithographically defined on top of the first metal layer, with larger openings which overlay the openings in the first layer of photoresist. The thickness of the gate electrode, and in one embodiment, the sections overlaying the drain and source electrodes, is then increased by plating gold into the openings in the second layer of photoresist.

REFERENCES:
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patent: 3590478 (1971-07-01), Takehana
patent: 3604107 (1971-09-01), Fassett
patent: 3669730 (1972-06-01), Lepselter
patent: 3672985 (1972-06-01), Nathanson et al.
patent: 3900344 (1975-08-01), Magdo
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patent: 4048712 (1977-09-01), Buiatti
A. K. Sinha, Metallization Scheme for n-GaAs Schottky Diodes Incorporating Sintered Contacts and a W Diffusion Barrier; Applied Physics Letters, vol. 26, No. 4 (2/1975) pp. 171-173.
P. A. Totta et al., Low Barrier Height Schottky Barrier Diodes by Metal RF Sputter Deposition Process; IBM Tech. Disc. Bulletin, vol. 20, No. 11B (4/1978) p. 4812.

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