Low resistance contact for high density integrated circuit

Details Low resistance contact for high density integrated circuit Low resistance contact for high density integrated circuit

1982-06-21

1984-05-01

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 148 15, 148187, 357 91, H01L 21265, B01J 1700

Patent

active

044452705

ABSTRACT:
A novel process for fabricating low resistance contacts for high density integrated circuits is described wherein during the initial processing of the device, after a scaled MOSFET is formed, contact openings, having vertical walls with respect to the underlying substrate, are provided. An apertured masking layer, having apertures which provide an open are a somewhat larger than the original contact opening, is formed on the structure after which, the structure is subjected to a high energy deep implant step followed by a low energy, shallow, supplemental implant step. The high energy implant serves to provide the device with a deep junction at the contact area to minimize spiking and, by reason of the shallow implant, good ohmic contact may be made. Since the oxide surrounding the contact opening is also implanted, there is provided means for tapering the edges of the contact opening.

REFERENCES:
patent: 4102733 (1978-07-01), Dela moneda
patent: 4114256 (1978-09-01), Thibault et al.
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4305760 (1981-12-01), Trudel
patent: 4306915 (1981-12-01), Shiba
patent: 4371403 (1983-02-01), Ikubo et al.
patent: 4404733 (1983-10-01), Sasaki

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