Low redundancy data RAM architecture for monolithic...

Details Low redundancy data RAM architecture for monolithic... Low redundancy data RAM architecture for monolithic...

2005-02-16

2008-11-11

Kizou, Hassan (Department: 2619)

Multiplex communications

Pathfinding or routing

Through a circuit switch

Reexamination Certificate

active

07450575

ABSTRACT:
A non-blocking time and space switch is provided, based on specific memory method functions, called replica representatives, which shows a much lower data redundancy compared with the common RAM based approach as a consequence of multiple replica representatives. This allows the monolithic implementation of high through put time space switches.

REFERENCES:
patent: 4470139 (1984-09-01), Munter
patent: 4667320 (1987-05-01), Onno et al.
patent: 5168492 (1992-12-01), Beshai et al.
patent: 5784369 (1998-07-01), Romiti et al.
patent: 6307852 (2001-10-01), Fisher et al.
patent: 6704307 (2004-03-01), Graves et al.
patent: 6876649 (2005-04-01), Beshai
patent: 7099583 (2006-08-01), Schafer et al.
patent: 2003/0053417 (2003-03-01), Munter et al.
patent: 2003/0137977 (2003-07-01), Suzaki
patent: 0 453 129 (1991-10-01), None
patent: 1073309 (2000-07-01), None
patent: 982089 (1982-12-01), None

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