Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Patent
1999-09-24
2000-08-01
Nelms, David
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
438131, 438217, 438215, H01L 2182
Patent
active
060965800
ABSTRACT:
A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.
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Han Liang-Kai
Hannon Robert
Iyer S. Sundar Kumar
Iyer Subramanian S.
Khare Mukesh V.
International Business Machines - Corporation
Nelms David
Schnurmann H. Daniel
Smith Bradley
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